Tian-Bo Deng, Yong Lian: Symmetry-based analytically closed-form design of variable fractional-delay FIR digital filters.
2004-2007
Peyman Arian, Tapio Saramäki, Adly T. Fam: A decomposition technique for cascaded IIR-like filter blocks generating linear-phase FIR filters.
2008-2011
Raija Lehto, Tapio Saramäki, Olli Vainio: Synthesis of narrowband linear-phase FIR filters with a piecewise-polynomial impulse response.
2012-2015
Dan Stiurca: A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13µ CMOS process.
2176-2179
René Krenz: Efficient computation of dominators in multiple-output circuit graphs.
2223-2226
Valentin Gies, Thierry M. Bernard, Alain Mérigot: Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor.
2227-2230
Dominic K. C. Ho, La-or Kovavisaruch: Modified Taylor-series method for source and receiver localization using TDOA measurements with erroneous receiver positions.
2295-2298
Bernhard Kuenzle, Leonard T. Bruton: A novel low-complexity spatio-temporal ultra wide-angle polyphase cone filter bank applied to sub-pixel motion discrimination.
2397-2400
Takao Hinamoto, Ken-ichi Iwata, Wu-Sheng Lu: Minimization of L/sub 2/-sensitivity for a class of 2D state-space digital filters subject to L/sub 2/-scaling constraints.
2401-2404
H. N. Nagaraja, Amit Patra, Debaprasad Kastha: Generalized analysis of integrated magnetic component based low voltage interleaved DC-DC buck converter for efficiency improvement.
2485-2489
K. C. Tam, Siu Chung Wong, Chi Kong Tse: Wavelet-based piecewise approximation of steady-state waveforms for power electronics circuits [power converter examples].
2490-2493
Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang: On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element].
2531-2534
Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli: Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed.
2543-2546
Hashem Zare-Hoseini, Izzet Kale: On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor Delta-Sigma modulators.
2547-2550
H. K. Kwan: Multi-output passive digital filters.
2595-2598
Mrinmoy Bhattacharya, Tapio Saramäki: Fourth-order structures for multiplierless realizations of bandpass and bandstop digital filters transformed from all-pole lowpass filters.
2599-2602
S. C. Chan, K. M. Tsui: Wordlength determination algorithms for hardware implementation of linear time invariant systems with prescribed output accuracy.
2607-2610
Vincent Knopik, Didier Belot, Baudouin Martineau: 20 dBm CMOS class AB power amplifier design for low cost 2 GHz-2.45 GHz consumer applications in a 0.13µm technology.
2675-2678
Tracey Y. Zhou, Tuna B. Tarim: An efficient and well-controlled IC system development flow: design approved specification and design guided test plan.
2775-2778
Masakazu Yagi, Takashi Hisakado, Kohshi Okumura: Algebraic representation of error bounds for describing function using Groebner base [nonlinear circuit analysis example].
2831-2834
Hoi-Kok Cheung, Wan-Chi Siu, David Dagan Feng: New block-based motion estimation for sequences with illumination variation and its application to video mosaicking.
2903-2906
Yueh-Yi Wang, Chun-Jen Tsai: An efficient dual-interpolator architecture for sub-pixel motion estimation.
2907-2910
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