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ORCIDSandip Tiwari
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2010 – 2019
- 2017
[c8]Sandip Tiwari, Damien Querlioz:
On the Physical Underpinnings of the Unusual Effectiveness of Probabilistic and Neural Computation. ICRC 2017: 1-4- 2015
- [j7]Sandip Tiwari:
Implications of Scales in Processing of Information. Proc. IEEE 103(8): 1250-1273 (2015) - 2014
- [j6]Jaeyoon Kim, Sandip Tiwari:
Inexact computing using probabilistic circuits: Ultra low-power digital processing. ACM J. Emerg. Technol. Comput. Syst. 10(2): 16:1-16:23 (2014) - 2012
- [j5]Jaeyoon Kim, Paul Michael Solomon, Sandip Tiwari:
Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(4): 806-819 (2012) - [c7]Sandip Tiwari:
Nanostructure devices for logic and memory and beyond. ESSDERC 2012: 28-35 - 2011
- [j4]Sang-Hyeon Lee, Moonkyung Mark Kim, Byung-ki Cheong, Jooyeon Kim, Jo-Won Lee, Sandip Tiwari:
A Single Element Phase Change Memory. IEICE Trans. Electron. 94-C(5): 676-680 (2011) - [c6]Jaeyoon Kim, Sandip Tiwari:
Inexact computing for ultra low-power nanometer digital circuit design. NANOARCH 2011: 24-31
2000 – 2009
- 2007
- [c5]Sandip Tiwari:
Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor. VLSI Design 2007: 24-25 - 2006
- [j3]Christianto C. Liu, Sandip Tiwari:
Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space. IEEE Trans. Circuits Syst. II Express Briefs 53-II(3): 207-211 (2006) - 2005
- [j2]Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari:
Bridging the Processor-Memory Performance Gapwith 3D IC Technology. IEEE Des. Test Comput. 22(6): 556-564 (2005) - [j1]Uygar Avci, Sandip Tiwari:
A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception. Microelectron. J. 36(1): 67-75 (2005) - [c4]Christianto C. Liu, Jeng-Huei Chen
, Rajit Manohar, Sandip Tiwari:
Mapping system-on-chip designs from 2-D to 3-D ICs. ISCAS (3) 2005: 2939-2942 - 2004
- [c3]Arvind Kumar, Sandip Tiwari:
Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics. DFT 2004: 280-288 - [c2]Arvind Kumar, Sandip Tiwari:
A power-performance adaptive low voltage analog circuit design using independently controlled double gate CMOS technology. ISCAS (1) 2004: 197-200 - [c1]Arvind Kumar, Sandip Tiwari:
Defect tolerance for nanocomputer architecture. SLIP 2004: 89-96
Coauthor Index
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