ICCD 1992:
Cambridge,
MA,
USA
Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992.
IEEE Computer Society 1992, ISBN 0-8186-3110-4 
@proceedings{DBLP:conf/iccd/1992,
title = {Proceedings 1991 IEEE International Conference on Computer Design:
VLSI in Computer {\&} Processors, ICCD '92, Cambridge, MA, USA,
October 11-14, 1992},
booktitle = {ICCD},
publisher = {IEEE Computer Society},
year = {1992},
isbn = {0-8186-3110-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Address
- Abbas El Gamal:
Field-Programmable Integrted Circuits - Overview and Future Trends.
2
Architecture Plenary
- Derrick Meyer:
Alpha Architecture: Hardware Implementation and Software Programming Implications.
4-5
CAD Plenary
Design and Test Plenary
Computer-Based Systems Plenary
Tutorial on Embedded Systems
Synthesis for Testability
Timing Analysis and Optimization
Design and Test of Multichip Modules
- Jeffery Banker:
Designing ASICs for Use with Multichip Modules.
54-58
- Yervant Zorian:
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan.
59-66
VLSI Design
Routing and Mapping in FPGAs
Computer Arithmetic
Computer-Based Systems
Panel Discussion
System Level Testing
Logic Synthesis for FPGAs
Special Purpose Architectures
- Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan:
MARVLE: A VLSI Chip for Variable Length Encoding and Decoding.
170-173
- Baher Haroun, Elie Torbey:
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks.
174-178
- G. Mahlich, G.-H. Huaman-Bollo, J. Preißner, Johannes Schuck, Hans Sahm, P. Weingart, D. Weinsziehr, J. Yeandel:
One-Chip System Integration for GSM with the DSP KISS-16V2.
179-182
Interconnect
CPUs
Interconnect Analysis
VLSI Technology /BiCMOS
System Level Verification and Test
Issues in Built-in-Self-Test
Timed Asynchronous Circuits
Scheduling in High-Level Synthesis
Architecture,
Verification,
and CAD Strategy of the NVAX Chip
Sequential Synthesis
- James Pardey, Tomasz Kozlowski, Jonathan Saul, Martin Bolton:
State Assignment Algorithms for Parallel Controller Synthesis.
316-319
- Maya K. Yajnik, Maciej J. Ciesielski:
Finite State Machine Decomposition Using Multiway Partitioning.
320-323
- June-Kyung Rho, Fabio Somenzi:
The Role of Prime Compatibles in the Minimization of Finite State Machines.
324-327
- Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Circuit Design Using Synthesis and Optimization.
328-333
Asynchronous Architectures
Test Generation and Fault Simulation
Floorplanning and Layout
ICCD Banquet
Asynchronous Control Circuits
- Alexandre Yakovlev:
On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits.
396-400
- Shlomo Kipnis:
Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line Busses.
401-406
- Tam-Anh Chu:
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications.
407-413
The Message Driven Processor
- William J. Dally, Andrew A. Chien, Stuart Fiske, Greg Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills:
The Message Driven Processor: An Integrated Multicomputer Processing Element.
416-419
- Peter R. Nuth, William J. Dally:
The J-Machine Network.
420-423
- Richard A. Lethin, William J. Dally:
MDP Design Tools and Methods.
424-428
Verification,
Validation,
and Test
Logic Synthesis I
Logic Synthesis II
Design of Fault-Tolerant and Self-Checking Circuits
Special Purpose Systems
Circuit and Switch Level Simulation
Formal Verification I
Environments for High-Level CAD
Memory Designs
Self-Testing and Repair of Memories
Formal Verification II
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