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ORCIDAlexander Albicki
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1990 – 1999
- 1996
[j5]Razak Hossain, Menghui Zheng, Alexander Albicki:
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 361-368 (1996)- [j4]Leszek D. Wronski, Razak Hossain, Alexander Albicki:
Extended hyperbolic congruential frequency hop code: generation and bounds for cross- and auto-ambiguity function. IEEE Trans. Commun. 44(3): 301-305 (1996) - 1995
- [c16]Yu Fang, Alexander Albicki:
Efficient testability enhancement for combinational circuit. ICCD 1995: 168-179 - [c15]Menghui Zheng, Alexander Albicki:
Low power and high speed multiplication design through mixed number representations. ICCD 1995: 566-576 - 1994
- [j3]Razak Hossain, Leszek D. Wronski, Alexander Albicki:
Low power design using double edge triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 261-265 (1994) - [j2]Andrzej Sobski, Alexander Albicki:
High Throughput Error Control Using Parallel CRC. VLSI Design 2(1): 33-50 (1994) - [c14]Razak Hossain, Menghui Zheng, Alexander Albicki:
Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering. ICCD 1994: 614-617 - [c13]Xiaodong Xie, Alexander Albicki:
New advances in path delay fault testing of combinational circuits. VTS 1994: 272-277 - 1993
- [c12]Stephen J. Muscato, Alexander Albicki:
Locally clocked microprocessor. Great Lakes Symposium on VLSI 1993: 47-51 - [c11]Xiaodong Xie, Alexander Albicki:
Bit-Splitting for Testability Enhancement in Scan-Based Design. ICCD 1993: 155-158 - [c10]Razak Hossain, Leszek D. Wronski, Alexander Albicki:
Double Edge Triggered Devices: Speed and Power Considerations. ISCAS 1993: 1491-1494 - 1992
- [c9]Brenda Luderman, Alexander Albicki:
An asynchronous multiplier. Great Lakes Symposium on VLSI 1992: 104-108 - [c8]John Compton, Alexander Albicki:
Self-timed pipeline with adder. Great Lakes Symposium on VLSI 1992: 109-113 - [c7]Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski:
Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. ICCD 1992: 482-485 - 1991
- [c6]Andrzej Krasniewski, Alexander Albicki:
Random Testability of Redundant Circuits. ICCD 1991: 424-427
1980 – 1989
- 1989
- [j1]Robert F. Molyneaux, Alexander Albicki:
Comments on "Ternary Scan Design for VLSI Testability". IEEE Trans. Computers 38(2): 256-263 (1989) - [c5]Christopher Bucci, Alexander Albicki:
An algorithm for voice and data integration on packet-switched local area networks. ICCD 1989: 156-159 - 1988
- [c4]Rajiv Arora, Alexander Albicki:
Prioritized access in CSMA networks: a node partitioning approach. LCN 1988: 275-280 - 1985
- [c3]Andrzej Krasniewski, Alexander Albicki:
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. DAC 1985: 808-811 - [c2]Andrzej Krasniewski, Alexander Albicki:
Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. ITC 1985: 362-371 - [c1]Carl Staelin, Alexander Albicki:
Evaluation ot Monitor Complexity for Concurrently Testing Microprogrammed Control Units. ITC 1985: 733-736
Coauthor Index
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