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  Petru Eles, Axel Jantsch, Reinaldo A. Bergamaschi (Eds.): Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005. ACM 2005 ISBN 1-59593-161-9

Tutorials

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  H. Peter Hofstee, Michael N. Day: Hardware and software architectures for the CELL processor. 1
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  Trevor N. Mudge: Performance and power analysis of computer systems. 2

Keynote

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  Mike Muller: The challenges of embedded system design. 3

"Systems in 2010"

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  Charlie Johnson, Jeff Welser: Future processors: flexible and modular. 4-6
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  C. John Glossner, Mayan Moudgill, Daniel Iancu, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Samori, Tanuj Raja, Michael J. Schulte, Stamatis Vassiliadis: Future wireless convergence platforms. 7-12
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  Jonathan Wilmot: A core flight software system. 13-14

Innovative synthesis methodologies and algorithms

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  Oliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn: Conflict analysis in multiprocess synthesis for optimized system integration. 15-20
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  Mehrdad Reshadi, Daniel Gajski: A cycle-accurate compilation algorithm for custom pipelined datapaths. 21-26
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  Vinu Vijay Kumar, John Lach: Highly flexible multi-mode system synthesis. 27-32

Software controlled memory systems

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  Xiangrong Zhou, Peter Petrov: Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors. 33-38
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  Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke: Automated data cache placement for embedded VLIW ASIPs. 39-44
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  Chuanjun Zhang: An efficient direct mapped instruction cache for application-specific embedded systems. 45-50

Techniques for code generation, partitioning and analysis

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  Hyunok Oh, Nikil D. Dutt, Soonhoi Ha: Shift buffering technique for automatic code synthesis from synchronous dataflow graphs. 51-56
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  Tomas Henriksson, Jeffrey Kang, Pieter van der Wolf: Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures. 57-62
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  Scott J. Weber, Kurt Keutzer: Using minimal minterms to represent programmability. 63-68

Network-on-chip architectures

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  Ümit Y. Ogras, Jingcao Hu, Radu Marculescu: Key research problems in NoC design: a holistic perspective. 69-74
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  Andreas Hansson, Kees Goossens, Andrei Radulescu: A unified approach to constrained mapping and routing on network-on-chip architectures. 75-80
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  Anthony Leroy, Paul Marchal, Adelina Shickova, Francky Catthoor, Frédéric Robert, Diederik Verkest: Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs. 81-86

Memory compression for embedded systems

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  Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin: Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. 87-92
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  Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar: CRAMES: compressed RAM for embedded systems. 93-98
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  Roberto Costa, Erven Rohou: Comparing the size of .NET applications with native code. 99-104

Voltage scaling and variability issues in system-level design

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  Fen Xie, Margaret Martonosi, Sharad Malik: Efficient behavior-driven runtime dynamic voltage scaling policies. 105-110
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  Alexander Maxiaguine, Samarjit Chakraborty, Lothar Thiele: DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. 111-116
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  Antonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor: A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. 117-122

Panel

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  Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser: What will system level design be when it grows up? 123

Application specific architectures

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  Wido Kruijtzer, Winfried Gehrke, Víctor Reyes, Ghiath Alkadi, Thomas Hinz, Jörn Jachalsky, Bruno Steux: The design of a smart imaging core for automotive and consumer applications: a case study. 124-129
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  Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede: Microcoded coprocessor for embedded secure biometric authentication systems. 130-135
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  Vida Kianzad, Sankalita Saha, Jason Schlessman, Gaurav Aggarwal, Shuvra S. Bhattacharyya, Wayne Wolf, Rama Chellappa: An architectural level design methodology for embedded face detection. 136-141

System-level power estimation and optimization

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  Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan: A power estimation methodology for systemC transaction level models. 142-147
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  Sankalp Kallakuri, Alex Doboli: Energy conscious online architecture adaptation for varying latency constraints in sensor network applications. 148-153
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  Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Aggregating processor free time for energy reduction. 154-159

Accelerating applications through customized instruction sets

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  Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J. Hum, Ramesh V. Peri, Jay Pickett: Enhanced code density of embedded CISC processors with echo technology. 160-165
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  Pan Yu, Tulika Mitra: Satisfying real-time constraints with custom instructions. 166-171
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  Kubilay Atasu, Günhan Dündar, Can C. Özturan: An integer linear programming approach for identifying instruction-set extensions. 172-177

Security-oriented application specific architectures

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  Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro: FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals. 178-183
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  Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano Gregori: Power-smart system-on-chip architecture for embedded cryptosystems. 184-189
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  Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Enhancing security through hardware-assisted run-time validation of program data properties. 190-195

BioChips and BioInformatics

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  Jacob White: Developing design tools for biological and biomedical applications of micro- and nano-technology. 196-200
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  Krishnendu Chakrabarty, Fei Su: System-level design automation tools for digital microfluidic biochips. 201-206
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  Robert S. Germain, Blake G. Fitch, Aleksandr Rayshubskiy, Maria Eleftheriou, Michael Pitman, Frank Suits, Mark Giampapa, T. J. Christopher Ward: Blue matter on blue gene/L: massively parallel computation for biomolecular simulation. 207-212

High-level techniques for specific applications

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  Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell: High-level synthesis for large bit-width multipliers on FPGAs: a case study. 213-218
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  Bo Yang, Ramesh Karri: Power optimization for universal hash function data path using divide-and-concatenate technique. 219-224
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  Peggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.: Efficient performance analysis of asynchronous systems based on periodicity. 225-230

Memory access and virtualization techniques for performance

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  Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard: SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. 231-236
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  Mehrdad Reshadi, Prabhat Mishra: Memory access optimizations in instruction-set simulators. 237-242
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  Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne: Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. 243-248

On-chip communication and interface design

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  Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. 249-254
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  Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski: Automatic network generation for system-on-chip communication design. 255-260
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  Adriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau, Wander O. Cesário, Ahmed Amine Jerraya: Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design. 261-266
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  Víctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Antonio Núñez, Wido Kruijtzer: A multicast inter-task communication protocol for embedded multiprocessor systems. 267-272

Algorithms and methodologies for new architectures

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  Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer: An automated exploration framework for FPGA-based soft multiprocessor systems. 273-278
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  Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild: FlexPath NP: a network processor concept with application-driven flexible processing paths. 279-284
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  Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth: Hardware/software partitioning of software binaries: a case study of H.264 decode. 285-290
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  Youngsoo Kim, Suleyman Sair: Designing real-time H.264 decoders with dataflow architectures. 291-296

SW vs. HW acceleration techniques

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  Seng Lin Shee, Sri Parameswaran, Newton Cheung: Novel architecture for loop acceleration: a case study. 297-302
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  Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado, Francky Catthoor: Improving superword level parallelism support in modern compilers. 303-308
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  Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha: Iterational retiming: maximize iteration-level parallelism for nested loops. 309-314

Prototyping and validation techniques

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  Jiwon Hahn, Qiang Xie, Pai H. Chou: Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems. 315-320
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  Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta: Dynamic phase analysis for cycle-close trace generation. 321-326
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  Edgar Leonardo Romero, Marius Strum, Wang Jiang Chau: Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. 327-332

Panel

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  Janos Sztipanovits, C. John Glossner, Trevor N. Mudge, Chris Rowen, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf, Feng Zhao: Grand challenges in embedded systems. 333