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Publication search results
found 62 matches
- 2005
- Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS 2005: 190-195 - Kubilay Atasu, Günhan Dündar, Can C. Özturan:
An integer linear programming approach for identifying instruction-set extensions. CODES+ISSS 2005: 172-177 - Oliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn:
Conflict analysis in multiprocess synthesis for optimized system integration. CODES+ISSS 2005: 15-20 - Krishnendu Chakrabarty, Fei Su:
System-level design automation tools for digital microfluidic biochips. CODES+ISSS 2005: 201-206 - Roberto Costa, Erven Rohou:
Comparing the size of .NET applications with native code. CODES+ISSS 2005: 99-104 - Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan:
A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147 - Robert S. Germain, Blake G. Fitch, Aleksandr Rayshubskiy, Maria Eleftheriou, Michael Pitman, Frank Suits, Mark Giampapa, T. J. Christopher Ward:
Blue matter on blue gene/L: massively parallel computation for biomolecular simulation. CODES+ISSS 2005: 207-212 - C. John Glossner, Mayan Moudgill, Daniel Iancu, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Samori, Tanuj Raja, Michael J. Schulte, Stamatis Vassiliadis:
Future wireless convergence platforms. CODES+ISSS 2005: 7-12 - Jiwon Hahn, Qiang Xie, Pai H. Chou:
Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems. CODES+ISSS 2005: 315-320 - Andreas Hansson, Kees Goossens, Andrei Radulescu:
A unified approach to constrained mapping and routing on network-on-chip architectures. CODES+ISSS 2005: 75-80 - Tomas Henriksson, Jeffrey Kang, Pieter van der Wolf:
Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures. CODES+ISSS 2005: 57-62 - H. Peter Hofstee, Michael N. Day:
Hardware and software architectures for the CELL processor. CODES+ISSS 2005: 1 - Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro:
FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals. CODES+ISSS 2005: 178-183 - Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer:
An automated exploration framework for FPGA-based soft multiprocessor systems. CODES+ISSS 2005: 273-278 - Charlie Johnson, Jeff Welser:
Future processors: flexible and modular. CODES+ISSS 2005: 4-6 - Sankalp Kallakuri, Alex Doboli:
Energy conscious online architecture adaptation for varying latency constraints in sensor network applications. CODES+ISSS 2005: 148-153 - Vida Kianzad, Sankalita Saha, Jason Schlessman, Gaurav Aggarwal, Shuvra S. Bhattacharyya, Wayne H. Wolf, Rama Chellappa:
An architectural level design methodology for embedded face detection. CODES+ISSS 2005: 136-141 - Youngsoo Kim, Suleyman Sair:
Designing real-time H.264 decoders with dataflow architectures. CODES+ISSS 2005: 291-296 - Wido Kruijtzer, Winfried Gehrke, Víctor Reyes, Ghiath Alkadi, Thomas Hinz, Jörn Jachalsky, Bruno Steux:
The design of a smart imaging core for automotive and consumer applications: a case study. CODES+ISSS 2005: 124-129 - Vinu Vijay Kumar, John C. Lach:
Highly flexible multi-mode system synthesis. CODES+ISSS 2005: 27-32 - Anthony Leroy, Paul Marchal, Adelina Shickova, Francky Catthoor, Frédéric Robert, Diederik Verkest:
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs. CODES+ISSS 2005: 81-86 - Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser:
What will system level design be when it grows up? CODES+ISSS 2005: 123 - Alexander Maxiaguine, Samarjit Chakraborty, Lothar Thiele:
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. CODES+ISSS 2005: 111-116 - Peggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.:
Efficient performance analysis of asynchronous systems based on periodicity. CODES+ISSS 2005: 225-230 - Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke:
Automated data cache placement for embedded VLIW ASIPs. CODES+ISSS 2005: 39-44 - Trevor N. Mudge:
Performance and power analysis of computer systems. CODES+ISSS 2005: 2 - Mike Muller:
The challenges of embedded system design. CODES+ISSS 2005: 3 - Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano Gregori:
Power-smart system-on-chip architecture for embedded cryptosystems. CODES+ISSS 2005: 184-189 - Ümit Y. Ogras, Jingcao Hu, Radu Marculescu:
Key research problems in NoC design: a holistic perspective. CODES+ISSS 2005: 69-74 - Hyunok Oh, Nikil D. Dutt, Soonhoi Ha:
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs. CODES+ISSS 2005: 51-56
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