CICC 2009: San Jose, California, USA

Session 1 - Keynote Presentation

• Thomas Williams:
  Another Inconvenient Truth: Snails Are More Intelligent Than Us.
  

Session 2 - Over-Sampled Data Converters

• Pavan Kumar Hanumolu, Alessandro Piovaccari:
  Over-sampled data converters.
  
• Tawfiq Musah, Sunwoo Kwon, Hasnain Lakdawala, Krishnamurthy Soumyanath, Un-Ku Moon:
  A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS. 1-4
  
• Mohammad Ranjbar, Arash Mehrabi, Omid Oliaei:
  A low-power 1.92MHz CT ΔΣ modulator with 5-bit successive approximation quantizer. 5-8
  
• Junpei Kamiishi, Yun-Shiang Shu, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
  A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator. 9-12
  
• Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks:
  A 120dB dynamic range 400mW class-D speaker driver with 4^th-order PWM modulator. 13-16
  

Session 3 - Biomedical Electronics

• Ed Lee:
  Biomedical electronics forum.
  

Session 4 - Nanoscale Power and Performance Optimizations

• Osamu Takahashi, Michael Seningen:
  Nanoscale power and performance optimizations.
  
• William Keshlear, Spence Oliver, Robert Colyer, Jeremy Schreiber, Ted Antoniadis, Tom Mickelson, Tim Puzey, Michael Bates:
  Design optimizations for reduced power and higher operating frequency in a custom x86-64 processor core. 17-20
  
• Kenji Shimazaki, Takaaki Okumura:
  A minimum decap allocation technique based on simultaneous switching for nanoscale SoC. 21-24
  
• Xiongfei Meng, Resve Saleh, Steven J. E. Wilton:
  Charge-borrowing decap: A novel circuit for removal of local supply noise violations. 25-28
  
• Dong Jiao, Jie Gu, Chris H. Kim:
  Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. 29-32
  
• Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
  Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test. 33-36
  

Session 5 - Frequency Synthesizers

• Cicero S. Vaucher, Rick Booth:
  Frequency Synthesizers.
  
• Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
  Insights into wideband fractional All-Digital PLLs for RF applications. 37-44
  
• Antonio Liscidini, Luca Vercesi, Rinaldo Castello:
  Time to digital converter based on a 2-dimensions Vernier architecture. 45-48
  
• Mark Ferriss, David T. Lin, Michael P. Flynn:
  A fractional-N PLL modulator with flexible direct digital phase modulation. 49-52
  
• Lei Lu, Lingbu Meng, Liang Zou, Hao Min, Zhangwen Tang:
  A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique. 53-56
  
• Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani:
  A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology. 57-60
  
• Enrico Monaco, Mattia Borgarino, Francesco Svelto, Andrea Mazzanti:
  A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output. 61-64
  

Session 6 - MEMS, Biomedical, and Sensors

• Hasnain Lakdawala, Kenneth Szajda:
  MEMS, biomedicals, and sensors.
  
• Farrokh Ayazi:
  MEMS for integrated timing and spectral processing. 65-72
  
• Amita C. Patil, Xiao-an Fu, Mehran Mehregany, Steven L. Garverick:
  Fully-monolithic, 600°C differential amplifiers in 6H-SiC JFET IC technology. 73-76
  
• Justin A. Richardson, Richard J. Walker, Lindsay Grant, David Stoppa, Fausto Borghetti, Edoardo Charbon, Marek Gersbach, Robert K. Henderson:
  A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging. 77-80
  
• Tamal Mukherjee, Gary K. Fedder:
  RF-CMOS-MEMS based frequency-reconfigurable amplifiers. 81-84
  
• Lorenzo Turicchia, Soumyajit Mandal, Maziar Tavakoli, Leon Fay, Vinith Misra, Jose L. Bohorquez, William R. Sanchez, Rahul Sarpeshkar:
  Ultra-low-power electronics for non-invasive medical monitoring. 85-92
  
• Edward K. F. Lee:
  High-voltage tolerant stimulation monitoring circuit in conventional CMOS process. 93-96
  
• Benoit Gosselin, Mohamad Sawan:
  Circuits techniques and microsystems assembly for intracortical multichannel ENG recording. 97-104
  

Session 7 - Gigabit Transceivers and Building Blocks

• Jin Liu, Jim Buckwalter:
  Gigabit transceivers and building blocks.
  
• Mike P. Li, Sergey Shumarayev:
  Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation. 105-112
  
• Hao Liu, Jin Liu, Robert Payne, Cy Cantrell, Mark Morgan:
  A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. 113-116
  
• Dong Hun Shin, Ji-Eun Jang, Frank O'Mahony, C. Patrick Yue:
  A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. 117-120
  
• Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti:
  A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation. 121-124
  
• Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani:
  A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. 125-128
  
• Shih-Hao Huang, Wei-Zen Chen:
  A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector. 129-132
  

Session 8 - CMOS Scaling and Beyond

• Takamaro Kikkawa, Jordan Lai:
  CMOS scaling and beyond.
  
• Burn J. Lin, R. G. Liu:
  Progress and outlook of lithography for semiconductor IC. 133-140
  
• Jeff Gambino, Fen Chen, John He:
  Copper interconnect technology for the 32 nm node and beyond. 141-148
  
• Manfred Horstmann, Andy Wei, Jan Hoentschel, Thomas Feudel, Thilo Scheiper, Rolf Stephan, Martin Gerhardt, Stephan Krügel, Michael Raab:
  Advanced SOI CMOS transistor technologies for high-performance microprocessor applications. 149-152
  
• Shinichi Takagi:
  High mobility channel CMOS technologies for realizing high performance LSI's. 153-160
  

Poster Session

• Ajay Kumar:
  Trimless second order curvature compensated bandgap reference using diffusion resistor. 161-164
  
• Abhijit Kumar Das, Hemant Bhasin, Sundara Siva Rao Giduturi:
  A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply. 165-168
  
• Lanny L. Lewyn, Markus Loose:
  A 1.5mW 16b ADC with improved segmentation and centroiding algorithms and litho-friendly physical design (LFD) used in space telescope imaging applications. 169-170
  
• Sunwoo Kwon, Pavan Kumar Hanumolu, Sang-Ho Kim, Sung-No Lee, Seung-Bin You, Ho-Jin Park, Jae-Whui Kim, Un-Ku Moon:
  An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. 171-174
  
• Michiko Tokumaru, Heiji Ikoma, Yuji Yamada, Kouji Okamoto, Akira Yamamoto, Yoshinori Shirakawa:
  A 14.6^th-order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems. 175-178
  
• Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri:
  64-bit prefix adders: Power-efficient topologies and design solutions. 179-182
  
• Bita Nezamfar, Mark Horowitz:
  Energy-performance tunable logic. 183-186
  
• Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
  A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. 187-190
  
• Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
  A 0.92mm² 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. 191-194
  
• Xueqiang Wang, Dong Wu, Chaohong Hu, Liyang Pan, Runde Zhou:
  Embedded high-speed BCH decoder for new-generation NOR flash memories. 195-198
  
• James Salvia, Pedram Lajevardi, Mohammad Hekmat, Boris Murmann:
  A 56MΩ CMOS TIA for MEMS applications. 199-202
  
• Kisoo Kim, Hokyu Lee, Sangdon Jung, Chulwoo Kim:
  A 366kS/s 400uW 0.0013mm² frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock. 203-206
  
• Dick James:
  Design-for-manufacturing features in nanometer logic processes - a reverse engineering perspective. 207-210
  
• Shih-Jung Wang, Yu-Huei Lee, Yung-Chih Lai, Ke-Horng Chen:
  Quadratic differential and integration technique in V² control buck converter with small ESR capacitor. 211-214
  
• Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
  Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. 215-218
  
• Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata:
  A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. 219-222
  
• Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu:
  An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction. 223-226
  
• Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu:
  Pathfinding for 22nm CMOS designs using Predictive Technology Models. 227-230
  
• Tae-Hyoung Kim, Wei Zhang, Chris H. Kim:
  An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. 231-234
  
• Rony E. Amaya, Cornelius J. Verver:
  A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler. 235-238
  
• Chethan Rao, Alvin Wang, Shaishav Desai:
  A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes. 239-242
  
• Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, ByeongHa Park, Chulwoo Kim:
  A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. 243-246
  
• Peng Yu, Zheng Gong, Ming Gu, Yin Shi, Foster F. Dai:
  A 430MHz-2.15GHz fractional-N frequency synthesizer for DVB and ABS-S applications. 247-250
  
• Stephen Horst, Stan Phillips, Hossein Miri Lavasani, Farrokh Ayazi, John D. Cressler:
  SiGe digital frequency dividers with reduced residual phase noise. 251-254
  
• Jongsik Kim, Seung Jun Lee, Seungsoo Kim, Jong Ok Ha, Junki Min, Yun Seong Eo, Hyunchol Shin:
  A 54-862 MHz CMOS direct conversion transceiver for IEEE 802.22 cognitive radio applications. 255-258
  
• Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos:
  A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. 259-262
  

Session 9 - Nyquist Rate ADC's

• Eric Naviasky, Ron Kapusta:
  Nyquist rate ADCs.
  
• Kailash Chandrashekar, Bertan Bakkaloglu:
  A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs. 263-266
  
• Adrian Leuciuc, William Evans, Honghao Ji, Eric Naviasky, Xinhua He:
  A 12-b 56MS/s pipelined ADC in 65nm CMOS. 267-270
  
• Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park:
  A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. 271-274
  
• David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
  A continuous-time input pipeline ADC with inherent anti-alias filtering. 275-278
  
• Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
  Split capacitor DAC mismatch calibration in successive approximation ADC. 279-282
  
• Masashi Kijima, Kenji Ito, Kuniyoshi Kamei, Sanroku Tsukamoto:
  A 6b 3GS/s flash ADC with background calibration. 283-286
  
• Jing Yang, Thura Lin Naing, Robert W. Brodersen:
  A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS. 287-290
  

Session 10 - Power Management

• Rajeevan Amirtharajah, Cory Arnold:
  Power management.
  
• Charles R. Sullivan:
  Integrating magnetics for on-chip power: Challenges and opportunities. 291-298
  
• Xiaocheng Jing, Philip K. T. Mok, Ming Chak Lee:
  A wide-load-range single-inductor-dual-output boost regulator with minimized cross-regulation by constant-charge-auto-hopping (CCAH) control. 299-302
  
• Weiwei Xu, Ye Li, Xiaohan Gong, Zhiliang Hong, Dirk Killat:
  A single-inductor dual-output switching converter with low ripples and improved cross regulation. 303-306
  
• Ying Wu, Sam Y. S. Tsui, Philip K. T. Mok:
  An area- and power-efficient monolithic Buck converter with fast transient response. 307-310
  
• Xiwen Zhang, Hoi Lee:
  An efficiency-enhanced auto-reconfigurable 2x/3x SC charge pump for transcutaneous power transmission. 311-314
  
• Tatsuya Matano, Koji Sato, Kiyoshi Nakai, Isamu Asano:
  A novel on-chip voltage generator for low voltage DRAMs and PRAMs. 315-318
  

Session 11 - Digital Wireline and PLL Techniques

• Gu-Yeon Wei, Afshin Momtaz:
  Digital wireline and PLL techniques.
  
• Amir Bashir, Jing Li, Kiran Ivatury, Naveed Khan, Nirav Gala, Noam Familia, Zulfiqar Mohammed:
  Fast lock scheme for phase-locked loops. 319-322
  
• Chih-Kong Ken Yang, E.-Hung Chen:
  ADC-based serial I/O receivers. 323-330
  
• Liangge Xu, Saska Lindfors, Kari Stadius, Jussi Ryynänen:
  A 2.4-GHz low-power all-digital phase-locked loop. 331-334
  
• Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
  A nonlinear phase detector for digital phase locked loops. 335-338
  
• Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel:
  Nonlinear behavior study in digital bang-bang PLL. 339-342
  
• Yehui Sun, Hui Wang:
  Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers. 343-346
  

Session 12 - Process Integration and Manufacturing Issues

• Philippe Jansen, David A. Sunderland:
  Process integration and manufacturing issues.
  
• Stefaan Decoutere, Stefaan Van Huylenbroeck, Bernd Heinemann, Alexander Fox, Pascal Chevalier, Alain Chantre, Thomas Meister, Klaus Aufinger, Michael Schröter:
  Pushing the speed limits of SiGe: C HBTs up to 0.5 Terahertz. 347-354
  
• Lloyd W. Condra, Stephan J. Meschter, Dave A. Pinsky, Anthony J. Rafanelli:
  The challenge of lead-free electronics for aerospace electronic systems. 355-362
  
• Raúl Andrés Bianchi, Christine Raynaud, Floria Blanchet, Frederic Monsieur, Olivier Noblanc:
  High voltage devices in advanced CMOS technologies. 363-370
  
• Albert Wang, Patrick R. Gill, Alyosha Molnar:
  Angle sensitive pixels in CMOS for lensless 3D imaging. 371-374
  

Session 13 - RF Transceivers and Building Blocks

• John Rogers, Aristotele Hadjichristo:
  RF transceivers and building blocks.
  
• Rui Yu, Theng-Tee Yeo, Kwang-Hung Tan, Shouxian Mou, Yike Cui, Haifeng Wang, Hwa-Seng Yap, Eugene Ting, Masaaki Itoh:
  A 5.5mA 2.4-GHz two-point modulation Zigbee transmitter with modulation gain calibration. 375-378
  
• Himanshu Khatri, Prasad S. Gudem, Lawrence E. Larson:
  A SAW-less CMOS CDMA receiver with active Tx filtering. 379-382
  
• Ganesh K. Balachandran, Raymond E. Barnett:
  A high dynamic range ASK demodulator for passive UHF RFID with automatic over-voltage protection and detection threshold adjustment. 383-386
  
• Tyson S. Wooten, Lawrence E. Larson:
  A 1 Watt 1-5 GHz Class B push-pull Si/SiGe HBT power amplifier. 387-390
  
• Behzad Razavi:
  Challenges in the design of cognitive radios¹. 391-398
  
• Yonghoon Song, Sungho Lee, Jaejun Lee, Sangwook Nam:
  A 29 dBm CMOS class-E power amplifier with 63% PAE using negative capacitance. 399-402
  
• Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu:
  CMOS RF transmitter with integrated power amplifier utilizing digital equalization. 403-406
  

Session 14 - Micro-Robotics and Energy Harvesting

• Gu Yeon Wu:
  Micro-robotics and energy harvesting forum.
  

Session 15 - Modeling of Passive Elements and Reliability

• Gennady Gildenblat, Hidetoshi Onodera:
  Modeling of passive elements and reliability.
  RF CMOS is more than CMOS: Modeling of RF passive components. 407-414 http: //dx.doi.org/10.1109/CICC.2009.5280811
• Karthik Balakrishnan, Duane S. Boning:
  Measurement and analysis of contact plug resistance variability. 415-422
  
• Yu Bi, Kees-Jan van der Kolk, Nick van der Meijs:
  Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors. 423-426
  
• Rui Zheng, Jyothi Velamala, Vijay Reddy, Varsha Balakrishnan, Evelyn Mintarno, Subhasish Mitra, Srikanth Krishnan, Yu Cao:
  Circuit aging prediction for low-power operation. 427-430
  
• Tanya Nigam:
  Impact of Transistor Level degradation on product reliability. 431-438
  

Session 16 - 3D ICs and 3D Systems

• Anne Marie Rincon, Alvin Loke:
  3D ICs and 3D systems.
  
• Rao R. Tummala, Venky Sundaram, Ritwik Chatterjee, P. Markodeya Raj, Nitesh Kumbhat, Vijay Sukumaran, Vikay Sridharan, Abhishek Choudury, Qiao Chen, Tapobrata Bandyopadhyay:
  Trend from ICs to 3D ICs to 3D systems. 439-444
  
• S. Simon Wong, Abbas El Gamal:
  The prospect of 3D-IC. 445-448
  
• Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
  47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. 449-452
  
• Joy Laskar, Stephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perumana, Matthew Leung, Debasis Dawn, David Yeh, Francesco Barale, Kevin Chuang, Gopal B. Iyer, Jong-Hoon Lee, Patrick Melet:
  60GHz CMOS/PCB co-design and phased array technology. 453-458
  
• Jeong-Hoon Cho, Hwan-Hee Lee, Jeong-Sik Moon:
  The highly integrated mobile WiMAX module using embedded PCB & SIP technology. 459-462
  
• Roberto Canegallo, Luca Perugini, Alberto Pasini, Massimiliano Innocenti, Mauro Scandiuzzo, Roberto Guerrieri, Pier Luigi Rolandi:
  System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface. 463-466
  

Poster Session

• E. K. F. Lee:
  A 3 - 14V rail-to-rail constant gm opamp in conventional 0.18µm CMOS process. 467-470
  
• J. Anders, P. SanGiorgio, G. Boero:
  An integrated CMOS receiver chip for NMR-applications. 471-474
  
• Jinghua Zhang, Libin Yao, Yong Lian:
  A 1.2-V 2.7-mW 160MHz continuous-time delta-sigma modulator with input-feedforward structure. 475-478
  
• Christopher D. LeBlanc, Benjamin T. Voegeli, Tian Xia:
  Dual-loop direct VCO modulation for spread spectrum clock generation. 479-482
  
• A. Goel, H. Hashemi:
  Phase noise in a synchronized concurrent dual-frequency oscillator. 483-486
  
• Ji-Hoon Kim, In-Cheol Park:
  A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE. 487-490
  
• Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen:
  Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis. 491-494
  
• Jingchao Wang, Chun Zhang, Baoyong Chi, Ziqiang Wang, Zhihua Wang:
  A fully integrated CMOS UHF RFID reader transceiver for handheld applications. 495-498
  
• Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic:
  A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. 499-502
  
• Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy:
  REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN. 503-506
  
• Wen-Sin Liew, Xiaodan Zou, Libin Yao, Yong Lian:
  A 1-V 60-µW 16-channel interface chip for implantable neural recording. 507-510
  
• Takashi Tokuda, Yoichi Takeuchi, Toshihiko Noda, Kiyotaka Sasagawa, Jun Ohta:
  CMOS-based flexible multi-site retinal stimulator toward retinal prosthesis technology. 511-514
  
• Kemal S. Demirci, Stuart B. Truax, Luke A. Beardslee, Oliver Brand:
  Chemical microsystem based on integration of microresonant sensor and CMOS ASIC. 515-518
  
• Ji-Hoon Park, Liang-Teck Pang, Kenneth Duong, Borivoje Nikolic:
  Fixed- and variable-length ring oscillators for variability characterization in 45nm CMOS. 519-522
  
• Ming-Hsin Huang, Yueh-Chang Tsai, Chun-Yu Hsieh, Ke-Horng Chen:
  An energy-recycling (ER) technique for field color sequential LCD backlight driving. 523-526
  
• Jiwei Fan, Xuening Li, Jinseok Park, Alex Chien-Lin Huang:
  A monolithic buck converter using differentially enhanced duty ripple control. 527-530
  
• Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara:
  Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. 531-534
  
• Massoud Tohidian, Ali Fotowat-Ahmady, Mahmoud Kamarei:
  A simplified method for phase noise calculation. 535-538
  
• Ming-Dou Ker, Yan-Liang Lin:
  Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices. 539-542
  
• Sander Gierkink, Kadaba Lakshmikumar, Vinod Mukundagiri, Drahoslav Lim, Arnold Muralt, Fred Larsen:
  A 3-level PWM ADSL2+ CO line driver. 543-546
  
• Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak:
  A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. 547-550
  
• Jae Hyuk Jang, Tae-Young Choi, Byunghoo Jung:
  A phase detector for 12.5Gbps clock and data recovery with optimal detection. 551-554
  
• Hayun Chung, Gu-Yeon Wei:
  Design-space exploration of backplane receivers with high-speed ADCs and digital equalization. 555-558
  
• Bodhisatwa Sadhu, Jaehyup Kim, Ramesh Harjani:
  A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO. 559-562
  
• Yu-Shiang Lin, Dennis Sylvester, David Blaauw:
  Near-field communication using phase-locking and pulse signaling for millimeter-scale systems. 563-566
  

Session 18 - Analog Techniques

• Sang-Soo Lee, Julian Tham:
  Analog techniques.
  
• John A. McNeill:
  Noise in short channel MOSFETs. 567-572
  
• Yoshinori Kusuda:
  Auto Correction Feedback for ripple suppression in a chopper amplifier. 573-576
  
• Mingoo Seok, Gyouho Kim, Dennis Sylvester, David Blaauw:
  A 0.5V 2.2pW 2-transistor voltage reference. 577-580
  
• Elyse Rosenbaum, Hyeon-Min Bae, Karan S. Bhatia, Adam C. Faust:
  Moving signals on and off chip. 585-592
  
• Armin Tajalli, Yusuf Leblebici:
  A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. 593-596
  

Session 19 - Test Methods and ICs for High-Speed Serdes

• Mike Li, Gordon Roberts:
  Test methods and ICs for high-speed serdes.
  
• Kwang-Ting Cheng, Hsiu-Ming Chang:
  Test strategies for adaptive equalizers. 597-604
  
• Alvin Leng Sun Loke, Bruce Andrew Doyle, Michael M. Oshima, Wade L. Williams, Robert G. Lewis, Charles Lin Wang, Audie Hanpachern, Karen M. Tucker, Prashanth Gurunath, Gladney C. Asada, Chad O. Lackey, Tin Tin Wee, Emerson S. Fang:
  Loopback architecture for wafer-level at-speed testing of embedded HyperTransport^TM processor links. 605-608
  
• Dennis Michael Fischette, Richard Joseph DeSantis, John H. Lee:
  An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI. 609-612
  

Session 20 - Circuit Simulation and Design Methodology

• Laurence Nagel, Colin McAndrew:
  Circuit simulation and design methodology.
  
• Jaeha Kim, Metha Jeeradit, ByongChan Lim, Mark A. Horowitz:
  Leveraging designer's intent: A path toward simpler analog CAD tools. 613-620
  
• Larry Smith, Shishuang Sun, Peter Boyle, Bozidar Krsnik:
  System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing. 621-628
  
• Rick E. Poore:
  GPU-accelerated time-domain circuit simulation. 629-632
  
• Dani Tannir, Roni Khazaka:
  Adjoint sensitivity analysis of nonlinear distortion in RF circuits. 633-636
  
• Sokratis D. Vamvakos, Vladimir Stojanovic, Borivoje Nikolic:
  Discrete-time, cyclostationary phase-locked loop model for jitter analysis. 637-640
  

Session 21 - SoC Architectures for Signal Processing

• Chau-Ching Chiong, Wei-Je Tzeng, Yuh-Jing Hwang, Wei-Ting Wong, Huei Wang, Ming-Tang Chen:
  SoC architectures for signal processing.
  
• Davide Rossi, Fabio Campi, Antonello Deledda, Simone Spolzino, Stefano Pucillo:
  A heterogeneous digital signal processor implementation for dynamically reconfigurable computing. 641-644
  
• Phi-Hung Pham, Phuong Mau, Chulwoo Kim:
  A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications. 645-648
  
• Minsu Kim, Joo-Young Kim, Seungjin Lee, Jinwook Oh, Hoi-Jun Yoo:
  A 54GOPS 51.8mW analog-digital mixed mode Neural Perception Engine for fast object detection. 649-652
  
• Tsung-Han Tsai, Chun-Nan Liu, Hsueh-Yi Lin, Hsing-Chuang Liu, Chia-Ying Wu:
  A 1.4 MHz 0.21 mW MPEG-2/4 AAC single chip decoder. 653-656
  

Session 22 - Millimeter-Wave ICs

• Ramesh Harjani, Alireza Shirvani Marvell:
  Millimeter-wave ICs.
  
• Dongha Shim, Chuying Mao, Ruonan Han, Swaminathan Sankaran, Eunyoung Seok, Changhua Cao, Wojciech Knap, Kenneth K. O:
  Paths to terahertz CMOS integrated circuits. 657-664
  
• Burak Çatli, Mona Mostafa Hella:
  A 60 GHz CMOS combined mm-wave VCO/divider with 10-GHz tuning range. 665-668
  
• Stefano Bozzola, Davide Guermandi, Federico Vecchi, Matteo Repossi, Massimo Pozzoni, Andrea Mazzanti, Francesco Svelto:
  A sliding IF receiver for mm-wave WLANs in 65nm CMOS. 669-672
  
• Rahul M. Kodkani, Lawrence E. Larson:
  A 24-GHz CMOS sub-harmonic mixer based zero-IF receiver with an improved active balun. 673-676
  
• Stefano Pellerano, Javier Alvarado Jr., Yorgos Palaskas:
  A mm-wave power harvesting RFID tag in 90nm CMOS. 677-680
  

Session 23 - ESD Design Challenges

• Manoj Sachdev, Hong-Ha Vuong:
  ESD design challenges.
  
• Shuqing Cao, Tze Wee Chen, Stephen G. Beebe, Robert W. Dutton:
  ESD design challenges and strategies in deeply-scaled integrated circuits. 681-688
  
• Ming-Dou Ker, Chang-Tzu Wang:
  Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS. 689-696
  
• Hossein Sarbishaei, Manoj Sachdev:
  ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology. 697-700
  

Session 24 - Memory Trends

• Vikas Chandra, Tom Andre:
  Memory trends.
  
• Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
  A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. 701-704
  
• Mudit Bhargava, Mark McCartney, Alexander Hoefler, Ken Mai:
  Low-overhead, digital offset compensated, SRAM sense amplifiers. 705-708
  
• Satyanand Nalam, Benton H. Calhoun:
  Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T. 709-712
  
• Peng Feng, Yunlong Li, Nanjian Wu:
  An ultra low power non-volatile memory in standard CMOS process for passive RFID tags. 713-716
  
• Jabeom Koo, Gil-Su Kim, Junyoung Song, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
  Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. 717-720
  

Last update Thu May 24 02:41:54 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page