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2010 – 2019
- 2019
[c6]Cagla Cakir, Andy W. Chen, Y. K. Chong, Sriram Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, Mudit Bhargava:
A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. VLSI Circuits 2019: 112-- 2014
- [b1]Mark P. McCartney:
SRAM Reliability Improvement Using ECC and Circuit Techniques. Carnegie Mellon University, USA, 2014 - 2013
- [c5]Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai
, Babak Falsafi:
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. PRDC 2013: 98-107 - 2011
- [c4]Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai:
FPGA-Based Solid-State Drive Prototyping Platform. FCCM 2011: 101-104 - [c3]Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai:
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA 2011: 284
2000 – 2009
- 2009
- [c2]Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai:
Low-overhead, digital offset compensated, SRAM sense amplifiers. CICC 2009: 705-708 - 2008
- [c1]Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi:
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC 2008: 415-418
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