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Publication search results
found 254 matches
- 2006
- Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
Three-dimensional place and route for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1132-1140 (2006) - Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical interconnect metrics for physical-design optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1273-1288 (2006) - Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 892-901 (2006) - Behzad Akbarpour, Sofiène Tahar:
An approach for the formal verification of DSP designs using Theorem proving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1441-1457 (2006) - Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi:
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2989-2996 (2006) - Hessa Al-Junaid, Tom J. Kazmierski, Peter R. Wilson, Jerzy Baranowski:
Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2757-2764 (2006) - Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris:
Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1547-1554 (2006) - Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1140-1145 (2006) - Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White:
FFTSVD: A Fast Multiscale Boundary-Element Method Solver Suitable for Bio-MEMS and Biomolecule Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(2): 274-284 (2006) - Jason Helge Anderson, Farid N. Najm:
Active leakage power optimization for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 423-437 (2006) - Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1146-1154 (2006) - Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury:
An integrated DFT solution for mixed-signal SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1368-1377 (2006) - Aditya Bansal, Bipul Chandra Paul, Kaushik Roy:
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2765-2774 (2006) - Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni:
Design-Intent Coverage - A New Paradigm for Formal Property Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1922-1934 (2006) - Anand S. Bedekar, Yi Wang, S. Krishnamoorthy, Sachin S. Siddhaye, Shankar Sundaram:
System-Level Simulation of Flow-Induced Dispersion in Lab-on-a-Chip Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(2): 294-304 (2006) - Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi:
Multilevel symmetry-constraint generation for retargeting large analog layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 945-960 (2006) - Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet:
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1950-1968 (2006) - Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni:
Defect Modeling Using Fault Tuples. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2450-2464 (2006) - Srinivas Bodapati, Farid N. Najm:
High-level current macro model for logic blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 837-855 (2006) - Karl-Friedrich Böhringer:
Modeling and Controlling Parallel Tasks in Droplet-Based Microfluidic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(2): 334-344 (2006) - Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh:
Optimal register sharing for high-level synthesis of SSA form programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 772-779 (2006) - Le Cai, Nathaniel Pettis, Yung-Hsiang Lu:
Joint Power Management of Memory and Disk Under Performance Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2697-2711 (2006) - Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie:
A Metric for Automatic Word-Length Determination of Hardware Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2228-2231 (2006) - M. Capobianchi, V. Labay, F. Shi, G. Mizushima:
Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2231-2241 (2006) - Josep Carmona, José Manuel Colom, Jordi Cortadella, Fernando García-Vallés:
Synthesis of asynchronous controllers using integer linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1637-1651 (2006) - Mario R. Casu, Luca Macchiarulo:
Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2996-3004 (2006) - Johann Cervenka, W. Wessner, E. Al-Ani, Tibor Grasser, Siegfried Selberherr:
Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential Equations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2118-2128 (2006) - Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee:
Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 79-91 (2006) - Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha:
Design Exploration With Imprecise Latency and Register Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2650-2662 (2006) - Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2894-2903 (2006)
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