"Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for ..."

Sébastien Bilavarn et al. (2006)

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DOI: 10.1109/TCAD.2005.862742

access: closed

type: Journal Article

metadata version: 2023-06-26

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Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet:
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1950-1968 (2006)

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