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Aiman H. El-Maleh
Person information
- affiliation: King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia
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2020 – today
- 2023
- [j36]Sadiq M. Sait
, Aiman El-Maleh, Mohammad Altakrouri, Ahmad Shawahna
:
Optimization of FPGA-based CNN accelerators using metaheuristics. J. Supercomput. 79(4): 4493-4533 (2023) - 2022
- [j35]Ahmad Shawahna
, Sadiq M. Sait
, Aiman El-Maleh
, Irfan Ahmad
:
FxP-QNet: A Post-Training Quantizer for the Design of Mixed Low-Precision DNNs With Dynamic Fixed-Point Representation. IEEE Access 10: 30202-30231 (2022) - [j34]Mahmoud Habboush
, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Saleh Alsaleh
:
DE-ZFP: An FPGA implementation of a modified ZFP compression/decompression algorithm. Microprocess. Microsystems 90: 104453 (2022) - [i3]Ahmad Shawahna, Sadiq M. Sait, Aiman El-Maleh, Irfan Ahmad:
FxP-QNet: A Post-Training Quantizer for the Design of Mixed Low-Precision DNNs with Dynamic Fixed-Point Representation. CoRR abs/2203.12091 (2022) - [i2]Sadiq M. Sait, Aiman El-Maleh, Mohammad Altakrouri, Ahmad Shawahna:
Optimization of FPGA-based CNN Accelerators Using Metaheuristics. CoRR abs/2209.11272 (2022) - 2021
- [j33]Aiman H. El-Maleh
, Ghashmi H. Bin Talib:
Time redundancy and gate sizing soft error-tolerant based adder design. Integr. 78: 49-59 (2021)
2010 – 2019
- 2019
- [j32]Ahmad Shawahna
, Sadiq M. Sait
, Aiman El-Maleh
:
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review. IEEE Access 7: 7823-7859 (2019) - [i1]Ahmad Shawahna, Sadiq M. Sait, Aiman El-Maleh:
FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review. CoRR abs/1901.00121 (2019) - 2018
- [j31]Ahmad T. Sheikh
, Aiman H. El-Maleh
:
Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits. J. Circuits Syst. Comput. 27(6): 1850097:1-1850097:17 (2018) - 2017
- [j30]Aiman H. El-Maleh
:
Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits. IET Comput. Digit. Tech. 11(4): 159-164 (2017) - [j29]Aiman H. El-Maleh
:
A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization. Integr. 56: 32-43 (2017) - [j28]Ahmad T. Sheikh
, Aiman H. El-Maleh
:
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing. Integr. 58: 35-46 (2017) - [j27]Ahmad T. Sheikh
, Aiman H. El-Maleh
, Muhammad E. S. Elrabaa, Sadiq M. Sait:
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 224-237 (2017) - 2016
- [j26]Sadiq M. Sait, Abubakar Bala
, Aiman H. El-Maleh
:
Cuckoo search based resource optimization of datacenters. Appl. Intell. 44(3): 489-506 (2016) - [j25]Aiman H. El-Maleh
:
Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits. IET Comput. Digit. Tech. 10(1): 30-36 (2016) - [j24]Muhammad E. S. Elrabaa, Amran Al-Aghbari
, Mohammed Alasli, Aiman El-Maleh
, Abdelhafid Bouhraoua, Mohammad R. Alshayeb
:
A low-cost platform for the prototyping and characterization of digital circuit IPs. Integr. 54: 1-9 (2016) - 2015
- [j23]Aiman H. El-Maleh
, Sadiq M. Sait, Abubakar Bala
:
State assignment for area minimization of sequential circuits based on cuckoo search optimization. Comput. Electr. Eng. 44: 13-23 (2015) - [j22]Mohammad R. Alshayeb
, Muhammad E. S. Elrabaa, Ayman Hroub, Amran Al-Aghbari
, Aiman H. El-Maleh
, Abdelhafid Bouhraoua:
Towards a Test Definition Language for Integrated Circuits. J. Circuits Syst. Comput. 24(3): 1550027:1-1550027:19 (2015) - [j21]Aiman H. El-Maleh
, Khaled A. Daud:
Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits. IEEE Trans. Reliab. 64(3): 935-948 (2015) - [c29]Aiman H. El-Maleh
:
A sequential circuit fault tolerance technique with enhanced area and power. ISSPIT 2015: 301-304 - [c28]Aiman H. El-Maleh
:
State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm. ISSPIT 2015: 305-308 - 2014
- [j20]Aiman H. El-Maleh
, Feras Chikh Oughali:
A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits. Microelectron. Reliab. 54(1): 316-326 (2014) - [j19]Aiman H. El-Maleh
, Ayed S. Al-Qahtani:
A finite state machine based fault tolerance technique for sequential circuits. Microelectron. Reliab. 54(3): 654-661 (2014) - 2013
- [j18]Aiman H. El-Maleh
, Ahmad T. Sheikh
, Sadiq M. Sait:
Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits. Appl. Soft Comput. 13(12): 4832-4840 (2013) - [c27]Aiman H. El-Maleh
, Feras Chikh Oughali:
Enhancing Reliability of Combinational Circuits against Soft Errors by Using a Generalized Modular Redundancy Scheme. ISED 2013: 62-66 - 2012
- [j17]Wenfa Zhan, Aiman El-Maleh
:
A new scheme of test data compression based on equal-run-length coding (ERLC). Integr. 45(1): 91-98 (2012) - 2011
- [j16]Aiman El-Maleh
, Saif al Zahir, Esam Khan:
Test data compression based on geometric shapes. Comput. Electr. Eng. 37(3): 376-391 (2011) - 2010
- [j15]Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh
:
A scheme of test data compression based on coding of even bits marking and selective output inversion. Comput. Electr. Eng. 36(5): 969-977 (2010)
2000 – 2009
- 2009
- [j14]Aiman H. El-Maleh
, Mustafa Imran Ali, Ahmad A. Al-Yamani:
Reconfigurable broadcast scan compression using relaxation-based test vector decomposition. IET Comput. Digit. Tech. 3(2): 143-161 (2009) - [j13]Aiman H. El-Maleh
, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan
:
Defect-tolerant n2-transistor structure for reliable nanoelectronic designs. IET Comput. Digit. Tech. 3(6): 570-580 (2009) - [c26]Wenfa Zhan, Aiman El-Maleh:
A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC). CSCWD 2009: 21-25 - 2008
- [j12]Esa Alghonaim, Aiman El-Maleh
, Mohamed Adnan Landolsi:
New Technique for Improving Performance of LDPC Codes in the Presence of Trapping Sets. EURASIP J. Wirel. Commun. Netw. 2008 (2008) - [j11]Aiman H. El-Maleh
:
Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput. Digit. Tech. 2(3): 155-163 (2008) - [j10]Aiman H. El-Maleh
:
Efficient test compression technique based on block merging. IET Comput. Digit. Tech. 2(5): 327-335 (2008) - [c25]Aiman H. El-Maleh
, Bashir M. Al-Hashimi, Aissa Melouki:
Transistor-level based defect tolerance for reliable nanoelectronics. AICCSA 2008: 53-60 - [c24]Esa Alghonaim, Aiman El-Maleh
, Mohamed Adnan Landolsi:
Using input/output queues to increase LDPC decoder performance. AICCSA 2008: 304-308 - 2007
- [j9]Aiman El-Maleh
, S. Saqib Khursheed:
Efficient test compaction for combinational circuits based on Fault detection count-directed clustering. IET Comput. Digit. Tech. 1(4): 364-368 (2007) - [c23]Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani:
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos. ATS 2007: 91-94 - 2006
- [j8]Sadiq M. Sait
, Aiman H. El-Maleh
, Raslan H. Al-Abaji:
Evolutionary algorithms for VLSI multi-objective netlist partitioning. Eng. Appl. Artif. Intell. 19(3): 257-268 (2006) - [j7]Aiman H. El-Maleh
, S. Saqib Khursheed, Sadiq M. Sait
:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2556-2564 (2006) - [c22]Aiman El-Maleh:
An efficient test vector compression technique based on block merging. ISCAS 2006 - [c21]Aiman H. El-Maleh, Sadiq M. Sait, F. Nawaz Khan:
Finite state machine state assignment for area and power minimization. ISCAS 2006 - 2005
- [c20]Aiman H. El-Maleh
, S. Saqib Khursheed, Sadiq M. Sait
:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. Asian Test Symposium 2005: 378-385 - 2004
- [j6]Aiman H. El-Maleh
, Khaled Al-Utaibi
:
An efficient test relaxation technique for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 933-940 (2004) - 2003
- [j5]Aiman H. El-Maleh
, Yahya E. Osais:
Test vector decomposition-based static compaction algorithms for combinational circuits. ACM Trans. Design Autom. Electr. Syst. 8(4): 430-459 (2003) - [c19]Sadiq M. Sait, Aiman H. El-Maleh
, Raslan H. Al-Abaji:
Enhancing performance of iterative heuristics for VLSI netlist partitioning. ICECS 2003: 507-510 - [c18]Aiman H. El-Maleh
:
A hybrid test compression technique for efficient testing of systems-on-a-chip. ICECS 2003: 599-602 - [c17]Yahya E. Osais, Aiman H. El-Maleh
:
A static test compaction technique for combinational circuits based on independent fault clustering. ICECS 2003: 1316-1319 - [c16]Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji:
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. ISCAS (5) 2003: 457-460 - [c15]Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji:
General iterative heuristics for VLSI multiobjective partitioning. ISCAS (5) 2003: 497-500 - [c14]Aiman H. El-Maleh, Khaled Al-Utaibi:
On efficient extraction of partially specified test sets for synchronous sequential circuits. ISCAS (5) 2003: 545-548 - [c13]Aiman H. El-Maleh
, Khaled Al-Utaibi
:
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. VTS 2003: 179-185 - 2002
- [c12]Aiman H. El-Maleh
, Raslan H. Al-Abaji:
Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression. ICECS 2002: 449-452 - [c11]Aiman El-Maleh
, Ali Al-Suwaiyan:
An efficient test relaxation technique for combinational circuits based on critical path tracing. ICECS 2002: 461-465 - [c10]Aiman El-Maleh
, Ali Al-Suwaiyan:
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. VTS 2002: 53-59 - 2001
- [c9]Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh
:
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. ICCD 2001: 484-487 - [c8]Saif al Zahir, Aiman El-Maleh, Esam Khan:
An efficient test vector compression technique based on geometric shapes [system-on-a-chip]. ICECS 2001: 1561-1564 - [c7]Aiman H. El-Maleh
, Yahya E. Osais:
A retiming-based test pattern generator design for built-in self test of data path architectures. ISCAS (4) 2001: 550-553 - [c6]Aiman El-Maleh, Esam Khan, Saif al Zahir:
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. VTS 2001: 54-61
1990 – 1999
- 1998
- [c5]Aiman H. El-Maleh, Mark Kassab, Janusz Rajski:
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC 1998: 625-631 - 1997
- [j4]Aiman H. El-Maleh
, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 528-543 (1997) - 1996
- [j3]Thomas E. Marchok, Aiman H. El-Maleh
, Wojciech Maly, Janusz Rajski:
A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1409-1423 (1996) - 1995
- [j2]Thomas E. Marchok, Aiman H. El-Maleh
, Janusz Rajski, Wojciech Maly:
Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. 12(2): 32-39 (1995) - [j1]Aiman H. El-Maleh
, Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 582-590 (1995) - [c4]Aiman H. El-Maleh
, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
On Test Set Preservation of Retimed Circuits. DAC 1995: 176-182 - [c3]Thomas E. Marchok, Aiman El-Maleh
, Wojciech Maly, Janusz Rajski:
Complexity of sequential ATPG. ED&TC 1995: 252-261 - 1994
- [c2]Aiman El-Maleh, Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. VTS 1994: 15-21 - 1992
- [c1]Janusz Rajski, Jagadeesh Vasudevamurthy, Aiman El-Maleh
:
Recent advances in logic synthesis with testability. VTS 1992: 254-256
Coauthor Index
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