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"Time redundancy and gate sizing soft error-tolerant based adder design."

Aiman H. El-Maleh, Ghashmi H. Bin Talib (2021)

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DOI: 10.1016/J.VLSI.2021.01.001

access: closed

type: Journal Article

metadata version: 2021-10-14

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  - journals/integration/El-MalehT21
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  - https://dblp.org/rec/journals/integration/El-MalehT21
Aiman H. El-Maleh, Ghashmi H. Bin Talib:
Time redundancy and gate sizing soft error-tolerant based adder design. Integr. 78: 49-59 (2021)

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