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"Modeling the computational efficiency of 2-D and 3-D silicon processors ..."

Matthew Grange et al. (2011)

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DOI: 10.1109/ICCAD.2011.6105347

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa:
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317

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