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2020 – today
- 2024
[c10]Yazhou Zu, Alireza Ghaffarkhah, Hoang-Vu Dang, Brian Towles, Steven Hand, Safeen Huda, Adekunle Bello, Alexander Kolbasov, Arash Rezaei, Dayou Du, Steve Lacy, Hang Wang, Aaron Wisner, Chris Lewis, Henri Bahini:
Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer. NSDI 2024: 761-774- [i2]Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah:
ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. CoRR abs/2406.16635 (2024) - 2022
- [c9]Dan Zhang
, Safeen Huda, Ebrahim M. Songhori, Kartik Prabhu, Quoc V. Le, Anna Goldie, Azalia Mirhoseini:
A full-stack search technique for domain optimized deep learning accelerators. ASPLOS 2022: 27-42 - [c8]Paras Jain, Safeen Huda, Martin Maas, Joseph E. Gonzalez, Ion Stoica, Azalia Mirhoseini:
Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers. DATE 2022: 184-189 - 2021
- [i1]Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Quoc V. Le, Anna Goldie, Azalia Mirhoseini:
A Full-stack Accelerator Search Technique for Vision Applications. CoRR abs/2105.12842 (2021) - 2020
- [j5]Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1378-1391 (2020)
2010 – 2019
- 2017
- [j4]Safeen Huda, Jason Helge Anderson:
Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2307-2320 (2017) - 2016
- [j3]S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson:
Hybrid LUT/Multiplexer FPGA Logic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1280-1292 (2016) - [c7]Safeen Huda, Jason Helge Anderson:
Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA 2016: 90-99 - [c6]Safeen Huda, Jason Helge Anderson:
Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. ISPD 2016: 123-130 - 2014
- [j2]Aynaz Vatankhahghadim, Safeen Huda, Ali Sheikholeslami:
A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2634-2643 (2014) - [c5]Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
On Hard Adders and Carry Chains in FPGAs. FCCM 2014: 52-59 - [c4]Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Optimizing effective interconnect capacitance for FPGA power reduction. FPGA 2014: 11-20 - 2013
- [j1]Safeen Huda, Ali Sheikholeslami:
A Novel STT-MRAM Cell With Disturbance-Free Read Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1534-1547 (2013) - [c3]Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Charge recycling for power reduction in FPGA interconnect. FPL 2013: 1-8 - 2010
- [c2]David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki:
Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. ISSCC 2010: 256-257
2000 – 2009
- 2009
- [c1]Safeen Huda, Muntasir Mallick, Jason Helge Anderson:
Clock gating architectures for FPGA power reduction. FPL 2009: 112-118
Coauthor Index
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