"Optimizing effective interconnect capacitance for FPGA power reduction."

Safeen Huda, Jason Helge Anderson, Hirotaka Tamura (2014)

> Home

Details and statistics

DOI: 10.1145/2554688.2554788

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/HudaAT14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/HudaAT14
Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Optimizing effective interconnect capacitance for FPGA power reduction. FPGA 2014: 11-20

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.