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ORCIDAjay Kumar Verma
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2020 – today
- 2021
[j7]Kushal Veer Singh
, Ajay Kumar Verma, Lovekesh Vig:
Deep learning based network similarity for model selection. Data Sci. 4(2): 63-83 (2021)
2010 – 2019
- 2012
- [c21]C. Patvardhan, Ajay Kumar Verma, C. Vasantha Lakshmi:
Document image binarization using wavelets for OCR applications. ICVGIP 2012: 60 - 2010
- [b1]Ajay Kumar Verma:
Pre-Synthesis Optimization of Arithmetic Circuits. EPFL, Switzerland, 2010 - [j6]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 341-354 (2010) - [j5]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1096-1109 (2010) - [j4]Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 578-590 (2010) - [c20]T. V. Vijay Kumar, Vikram Singh, Ajay Kumar Verma:
Generating Distributed Query Processing Plans Using Genetic Algorithm. DSDE 2010: 173-177 - [c19]Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24
2000 – 2009
- 2009
- [j3]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. 13(1-2): 115-137 (2009) - [j2]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [c18]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218 - [c17]Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209 - [c16]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD 2009: 797-804 - [c15]Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne:
Arithmetic optimization for custom instruction set synthesis. SASP 2009: 54-57 - 2008
- [j1]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1761-1774 (2008) - [c14]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339 - [c13]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255 - [c12]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - 2007
- [c11]Ajay Kumar Verma, Paolo Ienne:
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ASP-DAC 2007: 601-608 - [c10]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134 - [c9]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217 - [c8]Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 - [c7]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409 - [c6]Ajay Kumar Verma, Paolo Ienne:
Automatic synthesis of compressor trees: reevaluating large counters. DATE 2007: 443-448 - [c5]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179 - 2006
- [c4]Ajay Kumar Verma, Paolo Ienne:
Towards the automatic exploration of arithmetic-circuit architectures. DAC 2006: 445-450 - [c3]Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma:
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE 2006: 218-223 - 2004
- [c2]Paolo Ienne, Ajay Kumar Verma:
Arithmetic Transformations to Maximise the Use of Compressor Trees. DELTA 2004: 219-224 - [c1]Ajay Kumar Verma, Paolo Ienne:
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ICCAD 2004: 791-798
Coauthor Index
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