default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDPhilippe Roche
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[j13]Juan Suzano
, Fady Abouzeid, Giorgio Di Natale, Anthony Philippe, Philippe Roche:
On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations. IEEE Access 12: 29778-29794 (2024)- [j12]Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche:
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. J. Electron. Test. 40(3): 291-313 (2024) - [c38]Juan Suzano, Antoine Chastand, Emanuele Valea, Giorgio Di Natale, Anthony Philippe, Fady Abouzeid, Philippe Roche:
IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs. ETS 2024: 1-6 - [c37]Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Resilience Metric Characterization in Complex Digital Systems. ETS 2024: 1-4 - [c36]Esther Goudet, Luis Peña Treviño, Gutemberg G. dos Santos Júnior, Sayah El Hajji, Fabio Sureau, Lirida Naviner, Jean-Marc Daveau, Philippe Roche:
Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning. SBCCI 2024: 1-5 - 2023
- [c35]Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI 2023: 1-6 - [c34]Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche:
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. LATS 2023: 1-6 - 2022
- [c33]Tiziano Fiorucci, Giorgio Di Natale, Jean-Marc Daveau, Philippe Roche:
Software Product Reliability Based on Basic Block Metrics Recomposition. IOLTS 2022: 1-5 - 2021
- [c32]Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain:
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT 2021: 1-6 - [c31]Tiziano Fiorucci, Jean-Marc Daveau, Giorgio Di Natale, Philippe Roche:
Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems. IOLTS 2021: 1-6
2010 – 2019
- 2019
- [j11]Laurent Hoffer, Magali Saez-Ayala, Dragos Horvath, Alexandre Varnek, Xavier Morelli, Philippe Roche:
CovaDOTS: In Silico Chemistry-Driven Tool to Design Covalent Inhibitors Using a Linking Strategy. J. Chem. Inf. Model. 59(4): 1472-1485 (2019) - 2018
- [j10]Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran:
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits 53(7): 2088-2100 (2018) - [c30]Guenole Lallement, Fady Abouzeid, Thierry Di Gilio, Philippe Roche, Jean-Luc Autran:
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI. A-SSCC 2018: 197-200 - [c29]Yvan Debizet, Guénolé Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran:
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States. ISCAS 2018: 1-5 - 2017
- [j9]Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Gilles Gasiot, Philippe Roche:
Multi-Poisson process analysis of real-time soft-error rate measurements in bulk 65 nm and 40 nm SRAMs. Microelectron. Reliab. 76-77: 53-57 (2017) - [c28]Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran:
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. A-SSCC 2017: 69-72 - [c27]Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran:
A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. ESSCIRC 2017: 153-162 - 2016
- [j8]Marie Jeanne Basse, Stéphane Betzi, Xavier Morelli, Philippe Roche:
2P2Idb v2: update of a structural database dedicated to orthosteric modulation of protein-protein interactions. Database J. Biol. Databases Curation 2016 (2016) - [c26]Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic:
On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. A-SSCC 2016: 125-128 - [c25]Fady Abouzeid, Christophe Bernicot, Sylvain Clerc, Jean-Marc Daveau, Gilles Gasiot, Daniel Noblet, Dimitri Soussan, Philippe Roche:
30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. ESSCIRC 2016: 37-40 - [c24]Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche:
A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. ISCAS 2016: 1206-1209 - 2015
- [j7]Jean-Luc Autran, Daniela Munteanu, Soilihi Moindjie, Tarek Saad Saoud, S. Sauze, Gilles Gasiot, Philippe Roche:
ASTEP (2005-2015): Ten years of soft error and atmospheric radiation characterization on the Plateau de Bure. Microelectron. Reliab. 55(9-10): 1506-1511 (2015) - [c23]Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche:
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC 2015: 108-111 - [c22]Gilles Gasiot, Dimitri Soussan, Jean-Luc Autran, Victor Malherbe, Philippe Roche:
Muons and thermal neutrons SEU characterization of 28nm UTBB FD-SOI and Bulk eSRAMs. IRPS 2015: 2 - [c21]Victor Malherbe, Gilles Gasiot, Dimitri Soussan, Aurelien Patris, Jean-Luc Autran, Philippe Roche:
Alpha soft error rate of FDSOI 28 nm SRAMs: Experimental testing and simulation analysis. IRPS 2015: 11 - [c20]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid, Sylvain Clerc, Lirida A. B. Naviner, Philippe Roche:
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS 2015: 12 - [c19]Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c18]Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester:
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC 2015: 1-3 - [c17]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche:
Partial triplication of a SPARC-V8 microprocessor using fault injection. LASCAS 2015: 1-4 - 2014
- [j6]Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Anis Feki, Sylvain Clerc, Lorenzo Ciampolini, Fabien Giner, Robin Wilson, Philippe Roche:
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. IEEE J. Solid State Circuits 49(7): 1499-1505 (2014) - [j5]Jean-Luc Autran, Daniela Munteanu, Philippe Roche, Gilles Gasiot:
Real-time soft-error rate measurements: A review. Microelectron. Reliab. 54(8): 1455-1476 (2014) - [j4]Jean-Luc Autran, Maximilien Glorieux, Daniela Munteanu, Sylvain Clerc, Gilles Gasiot, Philippe Roche:
Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits. Microelectron. Reliab. 54(9-10): 2278-2283 (2014) - [c16]Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack:
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [j3]Marie Jeanne Basse, Stéphane Betzi, Raphaël Bourgeas, Sofia Bouzidi, Bernard Chétrit, Véronique Hamon, Xavier Morelli, Philippe Roche:
2P2Idb: a structural database dedicated to orthosteric modulation of protein-protein interactions. Nucleic Acids Res. 41(Database-Issue): 824-827 (2013) - [c15]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson:
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c14]Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Sylvain Clerc, Lorenzo Ciampolini, Philippe Roche:
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. ESSCIRC 2013: 205-208 - 2012
- [c13]Fady Abouzeid, Sylvain Clerc, Bertrand Pelloux-Prayer, Fabrice Argoud, Philippe Roche:
28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. ESSCIRC 2012: 153-156 - [c12]Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Philippe Roche:
A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance. ESSCIRC 2012: 313-316 - [c11]Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Dimitri Soussan, Philippe Roche:
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. ICICDT 2012: 1-4 - 2011
- [c10]Sylvain Clerc, Fady Abouzeid, Fabrice Argoud, Abhay Kumar, Rajesh Kumar, Philippe Roche:
A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. ICECS 2011: 117-120 - [c9]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche:
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. IOLTS 2011: 98-103 - 2010
- [j2]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche:
Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Microelectron. Reliab. 50(9-11): 1215-1218 (2010) - [j1]Jean-Luc Autran, Daniela Munteanu, Philippe Roche, Gilles Gasiot, S. Martinie, S. Uznanski, S. Sauze, S. Semikh, Evgeny Yakushev, S. Rozov, Pia Loaiza, G. Warot, M. Zampaolo:
Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level. Microelectron. Reliab. 50(9-11): 1822-1831 (2010) - [c8]Oscar Bailan, Umberto Rossi, Anne Wantens, Jean-Marc Daveau, Salvatore Nappi, Philippe Roche:
Verification of soft error detection mechanism through fault injection on hardware emulation platform. DSN Workshops 2010: 113-118 - [c7]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche:
Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. ICECS 2010: 263-267
2000 – 2009
- 2008
- [c6]Pierre Vanhauwaert, Michele Portolan, Régis Leveugle, Philippe Roche:
Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. ICECS 2008: 113-116 - [c5]Philippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche:
Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS. IOLTS 2008: 46-48 - [c4]Mark Lysinger, François Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell:
A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS. ISQED 2008: 23-29 - 2006
- [c3]Pierre Vanhauwaert, Régis Leveugle, Philippe Roche:
A Flexible SoPC-based Fault Injection Environment. DDECS 2006: 192-197 - [c2]Tino Heijmen, Damien Giot, Philippe Roche:
Factors That Impact the Critical Charge of Memory Elements. IOLTS 2006: 57-62 - [c1]Pierre Vanhauwaert, Régis Leveugle, Philippe Roche:
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. VLSI-SoC 2006: 391-396
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-31 21:07 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
