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ORCIDMitchell A. Thornton
◀ ▷ joint publications with coauthor community group 1
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Publications
- 2024
[c100]Clayton A. Harper, Mitchell A. Thornton, Eric C. Larson:
Learnable Statistical Moments Pooling for Automatic Modulation Classification. ICASSP 2024: 8981-8985- [c99]Jessie M. Henderson, Elena R. Henderson, Clayton A. Harper, Hiva Shahoei, William V. Oxford, Eric C. Larson, Duncan L. MacFarlane, Mitchell A. Thornton:
A Photonic Physically Unclonable Function's Resilience to Multiple-Valued Machine Learning Attacks. ISMVL 2024: 161-166 - [i6]Jessie M. Henderson, Elena R. Henderson, Clayton A. Harper, Hiva Shahoei, William V. Oxford, Eric C. Larson, Duncan L. MacFarlane, Mitchell A. Thornton:
A Photonic Physically Unclonable Function's Resilience to Multiple-Valued Machine Learning Attacks. CoRR abs/2403.01299 (2024) - [i5]Elena R. Henderson, Jessie M. Henderson, Hiva Shahoei, William V. Oxford, Eric C. Larson, Duncan L. MacFarlane, Mitchell A. Thornton:
Designing a Photonic Physically Unclonable Function Having Resilience to Machine Learning Attacks. CoRR abs/2404.02440 (2024) - [i4]Elena R. Henderson, Jessie M. Henderson, William V. Oxford, Mitchell A. Thornton:
Automated Quantum Circuit Generation for Computing Inverse Hash Functions. CoRR abs/2404.17142 (2024) - 2023
- [c98]Matthew Lee, Clayton A. Harper, William Flinchbaugh, Eric C. Larson, Mitchell A. Thornton:
Impacts of Synthetically Generated Data on Trackformer-based Multi-Object Tracking. AIPR 2023: 1-7 - [c97]Joshua Sylvester, Matthew Lee, Daniel Canon Ellis, Mitchell A. Thornton, Eric C. Larson:
Using Time Series Clustering to Inform Multimodal CNN Architectures. AIPR 2023: 1-8 - [c96]Zechariah Wolf
, Eric Larson, Mitchell A. Thornton:
Data Leakage in Isolated Virtualized Enterprise Computing Systems. ICISSP 2023: 118-123 - [c95]Duncan L. MacFarlane, Hiva Shahoei, Ifeanyi G. Achu, Evan Stewart, William V. Oxford, Mitchell A. Thornton:
Multiple-Valued Logic Physically Unclonable Function in Photonic Integrated Circuits. ISMVL 2023: 184-189 - [i3]Clayton A. Harper, Mitchell A. Thornton, Eric C. Larson:
Automatic Modulation Classification with Deep Neural Networks. CoRR abs/2301.11773 (2023) - [i2]Andrew Havard, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton:
CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques. CoRR abs/2304.12503 (2023) - 2022
- [c94]Darrell L. Young, Mark Bigham, Mark Bradbury, Eric Larson, Mitchell A. Thornton:
SMU-DDI Cyber Autonomy Range. AIPR 2022: 1-5 - [c93]Matthew Lee, Joshua Sylvester, Sunjoli Aggarwal, Aviraj Sinha, Michael A. Taylor, Nathan Srirama, Eric C. Larson, Mitchell A. Thornton:
Side Channel Identification using Granger Time Series Clustering with Applications to Control Systems. ICISSP 2022: 290-298 - [c92]Xianshan Wen, Ruobing Hua, Jianye Liu, Tao Fu, Liang Fang, Xiaoran Wang, Mitchell A. Thornton, Ping Gui:
Controller Area Network (CAN) Bus Transceiver with Authentication Support. ISCAS 2022: 1328-1331 - [c91]Aviraj Sinha, Mitchell A. Thornton:
Quantum Multiple Valued Kernel Circuits. ISMVL 2022: 1-8 - [c90]Rob Oshana, Mitchell A. Thornton, Mike Caraman:
A Side Channel Attack Detection System Using Processor Core Events and a Support Vector Machine. MECO 2022: 1-8 - [c89]Michael A. Taylor, Eric C. Larson, Mitchell A. Thornton:
General Process Detection Through Physical Side Channel Characterization. SysCon 2022: 1-8 - [i1]Aviraj Sinha, Elena R. Henderson, Jessie M. Henderson, Mitchell A. Thornton:
Automated Quantum Memory Compilation with Improved Dynamic Range. CoRR abs/2211.09860 (2022) - 2021
- [c88]Clayton A. Harper, Aviraj Sinha, Mitchell A. Thornton, Eric C. Larson:
SNR-Boosted Automatic Modulation Classification. ACSCC 2021: 372-375 - [c87]Aviraj Sinha, Michael A. Taylor, Nathan Srirama, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton:
Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus. CCTA 2021: 693-700 - [c86]Michael A. Taylor, Eric C. Larson, Mitchell A. Thornton:
Rapid Ransomware Detection through Side Channel Exploitation. CSR 2021: 47-54 - [c85]Rob Oshana, Mitchell A. Thornton, Eric C. Larson, Xavier Roumegue:
Real-Time Edge Processing Detection of Malicious Attacks Using Machine Learning and Processor Core Events. SysCon 2021: 1-8 - 2020
- [j28]Kaitlin N. Smith, Mitchell A. Thornton:
Higher Dimension Quantum Entanglement Generators. ACM J. Emerg. Technol. Comput. Syst. 16(1): 3:1-3:21 (2020) - [j27]Xiaoran Wang, Tianwei Liu, Shita Guo, Mitchell A. Thornton, Ping Gui:
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 12-22 (2020) - [c84]Clayton A. Harper, Lauren Lyons, Mitchell A. Thornton, Eric C. Larson:
Enhanced Automatic Modulation Classification using Deep Convolutional Latent Space Pooling. ACSSC 2020: 162-165 - [c83]Kaitlin N. Smith, Duncan L. MacFarlane, Mitchell A. Thornton:
A Quantum Photonic TRNG based on Quaternary Logic. ISMVL 2020: 164-169 - [c82]Kaitlin N. Smith, Mitchell A. Thornton, D. Michael Miller:
Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms. ISMVL 2020: 259-264 - 2019
- [j26]Tyler Giallanza, Travis Siems, Elena Smith, Erik Gabrielsen, Ian Johnson, Mitchell A. Thornton, Eric C. Larson:
Keyboard Snooping from Mobile Phone Arrays with Mixed Convolutional and Recurrent Neural Networks. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 3(2): 45:1-45:22 (2019) - [c80]Kaitlin N. Smith, Mitchell A. Thornton:
Entangled State Preparation for Non-Binary Quantum Computing. ICRC 2019: 71-79 - [c79]Kaitlin N. Smith, Mitchell A. Thornton:
A quantum computational compiler and design tool for technology-specific targets. ISCA 2019: 579-588 - [c78]Kaitlin N. Smith, Mitchell A. Thornton:
Entanglement in Higher-Radix Quantum Systems. ISMVL 2019: 114-119 - [c77]Tyler Giallanza, Erik Gabrielsen, Michael A. Taylor, Eric C. Larson, Mitchell A. Thornton:
Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams. ISMVL 2019: 126-131 - [c76]Kaitlin N. Smith, Mitchell A. Thornton:
Quantum Logic Synthesis with Formal Verification. MWSCAS 2019: 73-76 - [c75]Kaitlin N. Smith, Mitchell A. Thornton:
Fixed Polarity Pascal Transforms with Symbolic Computer Algebra Applications. PACRIM 2019: 1-8 - 2018
- [j25]Kaitlin N. Smith, Tim LaFave, Duncan L. MacFarlane, Mitchell A. Thornton:
Higher-Radix Chrestenson Gates for Photonic Quantum Computation. FLAP 5(9): 1781-1798 (2018) - [c74]Micah Thornton, Mitchell A. Thornton:
Multiple-Valued Random Digit Extraction. ISMVL 2018: 162-167 - [c73]Kaitlin N. Smith, Tim LaFave, Duncan L. MacFarlane, Mitchell A. Thornton:
A Radix-4 Chrestenson Gate for Optical Quantum Computation. ISMVL 2018: 260-265 - 2017
- [c72]Mitchell A. Thornton, Duncan L. MacFarlane:
Quantum Photonic TRNG with Dual Extractor. QTOP@NetSys 2017: 171-182 - [c70]Kaitlin N. Smith, Michael A. Taylor, Anna A. Carroll, Theodore W. Manikas, Mitchell A. Thornton:
Automated Markov-chain based analysis for large state spaces. SysCon 2017: 1-8 - 2016
- [j23]Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler:
QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 86-99 (2016) - [c67]Philip C. Davis, Mitchell A. Thornton, Theodore W. Manikas:
Reliability block diagram extensions for non-parametric probabilistic analysis. SysCon 2016: 1-6 - 2015
- [j22]David Y. Feinstein, Mitchell A. Thornton:
Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables. J. Multiple Valued Log. Soft Comput. 24(1-4): 93-108 (2015) - [j21]Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein:
Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams. J. Multiple Valued Log. Soft Comput. 24(1-4): 135-149 (2015) - [c65]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. ISMVL 2015: 170-175 - 2014
- [j19]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. IEICE Trans. Inf. Syst. 97-D(9): 2234-2242 (2014) - [c64]Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Mitchell A. Thornton, Herman Lam, Victor P. Nelson:
Setting the stage for CE2016: A revised body of knowledge. FIE 2014: 1-4 - [c63]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. ISMVL 2014: 190-195 - [c62]Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama:
System Probability Distribution Modeling Using MDDs. ISMVL 2014: 196-201 - 2013
- [c61]Eric Durant, John Impagliazzo, Susan Conry, Andrew D. McGettrick, Mitchell A. Thornton, Timothy Wilson:
Computer engineering curriculum guidelines. FIE 2013: 1-2 - [c60]Mitchell A. Thornton, Theodore W. Manikas, Phillip A. Laplante:
Embedded and real-time systems classes in traditional and distance education format. FIE 2013: 1379-1385 - [c58]Mitchell A. Thornton, Theodore W. Manikas:
Spectral Response of Ternary Logic Netlists. ISMVL 2013: 109-116 - [c57]Mitchell A. Thornton, Jennifer Dworak:
Ternary Logic Network Justification Using Transfer Matrices. ISMVL 2013: 310-315 - [c56]Jason Moore, Mitchell A. Thornton, David W. Matula:
Low power floating-point multiplication and squaring units with shared circuitry. MWSCAS 2013: 1395-1398 - 2012
- [j16]David Y. Feinstein, Mitchell A. Thornton:
Reversible Logic Synthesis Based on Decision Diagram Variable Ordering. J. Multiple Valued Log. Soft Comput. 19(4): 325-339 (2012) - [c55]Robert B. Reese, Scott C. Smith, Mitchell A. Thornton:
Uncle - An RTL Approach to Asynchronous Design. ASYNC 2012: 65-72 - [c53]Theodore W. Manikas, David Y. Feinstein, Mitchell A. Thornton:
Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams. ISMVL 2012: 244-249 - [c52]David Y. Feinstein, Mitchell A. Thornton:
Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation. ISMVL 2012: 305-310 - [c51]John Impagliazzo, Susan Conry, Eric Durant, Andrew D. McGettrick, Mitchell A. Thornton, Timothy Wilson:
Computer engineering review task force report. SIGCSE 2012: 401-402 - 2011
- [c50]David Y. Feinstein, Mitchell A. Thornton:
On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams. ISMVL 2011: 164-169 - [c49]Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein:
Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities. ISMVL 2011: 263-267 - 2010
- [b5]Lun Li, Mitchell A. Thornton:
Digital System Verification: A Combined Formal Methods and Simulation Framework. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2010, ISBN 978-3-031-79814-6 - [c48]Satyendra R. Datla, Mitchell A. Thornton:
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits. ISMVL 2010: 128-133 - 2009
- [j14]David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics. J. Multiple Valued Log. Soft Comput. 15(4): 361-377 (2009) - [j13]Alex Fit-Florea, Lun Li, Mitchell A. Thornton, David W. Matula:
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures. IEEE Trans. Computers 58(2): 163-174 (2009) - [c47]Satyendra R. Datla, Mitchell A. Thornton, David W. Matula:
A Low Power High Performance Radix-4 Approximate Squaring Circuit. ASAP 2009: 91-97 - [c46]David Y. Feinstein, Mitchell A. Thornton:
On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering. ISMVL 2009: 132-138 - [c45]Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson:
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. ISMVL 2009: 256-261 - 2008
- [b4]D. Michael Miller, Mitchell Aaron Thornton:
Multiple Valued Logic - Concepts and Representations. Synthesis lectures on digital circuits and systems 12, Morgan & Claypool Publishers 2008, ISBN 978-1-59829-190-2, pp. I-XIII, 1-135 - [j12]Chad M. Lawler, Michael A. Harper, Stephen A. Szygenda, Mitchell A. Thornton:
Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility. Int. J. Bus. Inf. Syst. 3(3): 317-331 (2008) - [c44]Jason Moore, Mitchell A. Thornton, David W. Matula:
A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits. ACSCC 2008: 1819-1822 - [c43]David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. DATE 2008: 1378-1381 - [c42]David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ISMVL 2008: 138-143 - [c41]Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller:
Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL 2008: 202-207 - 2007
- [b3]D. Michael Miller, Mitchell A. Thornton:
Multiple Valued Logic: Concepts and Representations. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2007, ISBN 978-3-031-79778-1 - [j11]D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton:
QMDD Minimization Using Sifting for Variable Reordering. J. Multiple Valued Log. Soft Comput. 13(4-6): 537-552 (2007) - [c40]Lun Li, Frank P. Coyle, Mitchell A. Thornton:
Automatic High Level Assertion Generation and Synthesis for Embedded System Design. FDL 2007: 261-267 - [c39]David Y. Feinstein, V. S. S. Nair, Mitchell A. Thornton:
Advances in Quantum Computing Fault Tolerance and Testing. HASE 2007: 369-370 - [c38]Chad M. Lawler, Michael A. Harper, Mitchell A. Thornton:
Components and Analysis of Disaster Tolerant Computing. IPCCC 2007: 380-386 - [c37]D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton:
Variable Reordering and Sifting for QMDD. ISMVL 2007: 10 - [c36]Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler:
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50 - 2006
- [b2]Robert B. Reese, Mitchell A. Thornton:
Introduction to Logic Synthesis using Verilog HDL. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2006, ISBN 978-3-031-79742-2 - [c35]Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula:
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions. ASAP 2006: 99-104 - [c34]D. Michael Miller, Mitchell A. Thornton, David Goodman:
A Decision Diagram Package for Reversible and Quantum Circuit Simulation. IEEE Congress on Evolutionary Computation 2006: 2428-2435 - [c33]Lun Li, Mitchell A. Thornton, David W. Matula:
A digit serial algorithm for the integer power operation. ACM Great Lakes Symposium on VLSI 2006: 302-307 - [c32]D. Michael Miller, Mitchell A. Thornton:
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. ISMVL 2006: 30 - [c31]Lun Li, Mitchell A. Thornton, Marek A. Perkowski:
A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form. ISMVL 2006: 33 - 2005
- [j10]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Coarse-Grain Phased Logic CPU. IEEE Trans. Computers 54(7): 788-799 (2005) - [j9]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger:
Early evaluation for performance enhancement in phased logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 532-550 (2005) - [c30]David W. Matula, Alex Fit-Florea, Mitchell Aaron Thornton:
Table Lookup Structures for Multiplicative Inverses Modulo 2k. IEEE Symposium on Computer Arithmetic 2005: 156-163 - [c28]Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula:
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k. ISVLSI 2005: 130-135 - [c27]Frank P. Coyle, Mitchell A. Thornton:
A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams. ITCC (1) 2005: 432-435 - 2004
- [j8]Mitchell A. Thornton, D. Michael Miller:
Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs. J. Multiple Valued Log. Soft Comput. 10(2): 189-202 (2004) - [c26]Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver:
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. ACM Great Lakes Symposium on VLSI 2004: 413-416 - [c25]Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda:
Test vector generation and classification using FSM traversals. ISCAS (5) 2004: 309-312 - [c24]Lun Li, Mitchell A. Thornton, Stephen A. Szygenda:
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. ISVLSI 2004: 32-38 - 2003
- [c23]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Coarse-Grain Phased Logic CPU. ASYNC 2003: 2-13 - [c22]Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese:
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. DATE 2003: 11096-11097 - [c20]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Fine-Grain Phased Logic CPU. ISVLSI 2003: 70-79 - 2002
- [j5]Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. VLSI Design 14(1): 53-64 (2002) - [c19]Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver:
Generalized Early Evaluation in Self-Timed Circuits. DATE 2002: 255-259 - [c18]Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183 - [c17]Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler:
Switching activity estimation of finite state machines for low power synthesis. ISCAS (4) 2002: 65-68 - [c16]Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend:
Chrestenson Spectrum Computation Using Cayley Color Graphs. ISMVL 2002: 123-129 - [c15]Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52 - [c14]Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li:
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. ISVLSI 2002: 83-88 - [c13]Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton:
Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS 2002: 143-148 - [c12]Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala:
On-line Error Detection in a Carry-free Adder. IWLS 2002: 251-254 - 2001
- [b1]Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller:
Spectral techniques in VLSI CAD. Kluwer 2001, ISBN 978-0-7923-7433-6, pp. I-XIII, 1-250 - [c11]Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler:
Low power optimization technique for BDD mapped circuits. ASP-DAC 2001: 615-621 - [c10]Mitchell A. Thornton, Rolf Drechsler:
Spectral decision diagrams using graph transformations. DATE 2001: 713-719 - [c9]Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. ICCD 2001: 18-23 - 2000
- [j4]A. Zuzek, Rolf Drechsler, Mitchell A. Thornton:
Boolean function representation and spectral characterization using AND/OR graphs. Integr. 29(2): 101-116 (2000) - [c8]Rolf Drechsler, Mitchell A. Thornton, David Wessels:
MDD-Based Synthesis of Multi-Valued Logic Networks. ISMVL 2000: 41-46 - [c7]Rolf Drechsler, Mitchell A. Thornton:
Computation of Spectral Information from Logic Netlists. ISMVL 2000: 53-58 - [c6]Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
A Method for Approximate Equivalence Checking. ISMVL 2000: 447-452 - 1999
- [j3]Mitchell A. Thornton, V. S. S. Nair:
Behavioral synthesis of combinational logic using spectral-based heuristics. ACM Trans. Design Autom. Electr. Syst. 4(2): 219-230 (1999) - [c4]Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler:
Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. DATE 1999: 758-759 - 1998
- [c3]David L. Andrews, Mitchell A. Thornton:
Integration of CAD tools and structured design principles in an undergraduate computer engineering curriculum. WCAE@ISCA 1998: 21 - 1997
- [c2]Mitchell A. Thornton, David L. Andrews:
Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures. HICSS (1) 1997: 566-575 - 1995
- [j1]Mitchell A. Thornton, V. S. S. Nair:
Efficient calculation of spectral coefficients and their applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1328-1341 (1995) - 1993
- [c1]Mitchell A. Thornton, V. S. S. Nair:
An iterative combinational logic synthesis technique using spectral information. EURO-DAC 1993: 358-363
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