16. FPL 2006: Madrid, Spain

• Ken McElvain:
  FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges. 1
  
• David J. Lau, Orion Pritchard:
  Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions. 1-6
  
• Ian Page:
  Academia to IPO - A Modern Odyssey. 1
  
• Mike Hutton:
  FPGA Architecture Design Methodology. 1
  
• Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford:
  Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs. 1-6
  
• Peter Alfke:
  Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications. 1
  
• Yongfeng Gu, Tom Van Court, Martin C. Herbordt:
  Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations. 1-8
  
• Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon:
  High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD. 1-6
  
• Mike Hutton, Yan Lin, Lei He:
  Placement and Timing for FPGAs Considering Variations. 1-7
  
• Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton:
  FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. 1-6
  
• Florian Stock, Andreas Koch:
  Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays. 1-6
  
• Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo:
  System Level Architecture Exploration for Reconfigurable Systems On Chip. 1-6
  
• Michael Gilroy, James Irvine:
  RAID 6 Hardware Acceleration. 1-6
  
• Fernando J. Álvarez, Álvaro Hernández, Jesús Ureña, Juan Jesús García, Ana Jiménez, P. Santa Teresa:
  Detection Module in a Complementary Set of Sequences-Based Pulse Compression System. 1-6
  
• Mariano Lopez Garcia, Enrique F. Canto Navarro:
  FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor. 1-5
  
• Julien Lamoureux, Steven J. E. Wilton:
  Activity Estimation for Field-Programmable Gate Arrays. 1-8
  
• Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton:
  Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. 1-8
  
• Phillip H. Jones, John W. Lockwood, Young H. Cho:
  A Thermal Management and Profiling Method for Reconfigurable Hardware Applications. 1-7
  
• Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer:
  Modular Partitioning for Incremental Compilation. 1-6
  
• Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell:
  Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description. 1-6
  
• Oliver Pell, Wayne Luk:
  Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information. 1-6
  
• Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart Preneel:
  Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor. 1-6
  
• Dries Schellekens, Bart Preneel, Ingrid Verbauwhede:
  FPGA Vendor Agnostic True Random Number Generator. 1-6
  
• Allen Michalski, Duncan A. Buell:
  A Scalable Architecture for RSA Cryptography on Large FPGAs. 1-8
  
• Thilo Pionteck, Roman Koch, Carsten Albrecht:
  Applying Partial Reconfiguration to Networks-On-Chips. 1-6
  
• Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
  On-FPGA Communication Architectures and Design Factors. 1-8
  
• Sujan Pandey, Manfred Glesner:
  Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. 1-6
  
• Andreas Schallenberg, Wolfgang Nebel, Frank Oppenheimer:
  OSSS+R: Modelling and Simulating Self-Reconfigurable Systems. 1-6
  
• Wenyin Fu, Katherine Compton:
  A Simulation Platform for Reconfigurable Computing Research. 1-7
  
• Pao-Ann Hsiung, Chun-Hsian Huang, Chih-Feng Liao:
  Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems. 1-6
  
• Christos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping:
  FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. 1-6
  
• C. K. Wong, Philip Heng Wai Leong:
  An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic. 1-6
  
• Oswaldo Cadenas, Graham M. Megson:
  Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor. 1-6
  
• Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner:
  Multitasking Support for Dynamically Reconfig Urable Systems. 1-6
  
• Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
  An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. 1-6
  
• David B. Thomas, Wayne Luk:
  Non-Uniform Random Number Generation Through Piecewise Linear Approximations. 1-6
  
• Jan Torben Weinkopf, Klaus Harbich, Erich Barke:
  Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. 1-6
  
• David de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro J. Gil:
  Fast Emulation of Permanent Faults in VLSI Systems. 1-6
  
• Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud:
  Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. 1-5
  
• Usama Malik, Oliver Diessel:
  The Entropy of FPGA Reconfiguration. 1-6
  
• Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
  Adaptive FPGAs: High-Level Architecture and a Synthesis Method. 1-8
  
• Michael T. Frederick, Arun K. Somani:
  Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics. 1-6
  
• George Ferizis, Hossam A. ElGindy:
  Mapping Recursive Functions to Reconfigurable Hardware. 1-6
  
• Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
  A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. 1-6
  
• Chidamber Kulkarni, Gordon J. Brebner:
  Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. 1-6
  
• Kenji Kanazawa, Tsutomu Maruyama:
  An FPGA Solver for Large SAT Problems. 1-6
  
• K. S. Tham, Douglas L. Maskell:
  Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. 1-6
  
• Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-ichi Suzuki, Tadao Nakamura, Nobuyuki Ohba:
  Ray Tracing Hardware System Using Plane-Sphere Intersections. 1-6
  
• Hristo Nikolov, Todor Stefanov, Ed F. Deprettere:
  Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. 1-6
  
• Manuel Saldaña, Paul Chow:
  TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. 1-6
  
• Andreas Fidjeland, Wayne Luk:
  Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming. 1-6
  
• Guillermo Marcus Martinez, Gerhard Lienhart, Andreas Kugel, Reinhard Männer:
  On Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware. 1-6
  
• Hayden Kwok-Hay So, Robert W. Brodersen:
  Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. 1-6
  
• Pengyuan Yu, Patrick Schaumont:
  Executing Hardware as Parallel Software for Picoblaze Networks. 1-6
  
• Ling Zhuo, Viktor K. Prasanna:
  High-Performance and Parameterized Matrix Factorization on FPGAs. 1-6
  
• Goncalo M. de Matos, Horácio C. Neto:
  On Reconfigurable Architectures for Efficient Matrix Inversion. 1-6
  
• Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong:
  FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. 1-6
  
• Nastaran Baradaran, Pedro C. Diniz:
  Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures. 1-6
  
• Konstantinos Masselos, George A. Constantinides, Qiang Liu:
  Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. 1-6
  
• Tom Van Court, Martin C. Herbordt:
  Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique. 1-7
  
• Dionisios N. Pnevmatikatos, Aggelos Arelakis:
  Variable-Length Hashing for Exact Pattern Matching. 1-6
  
• G. Adam Covington, Charles L. G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho:
  High Speed Document Clustering in Reconfigurable Hardware. 1-7
  
• Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jung:
  Regular Expression Software Deceleration for Intrusion Detection Systems. 1-8
  
• Luis G. Barbero, John S. Thompson:
  FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems. 1-6
  
• Imran Ahmed, Tughrul Arslan:
  A Reconfigurable Viterbi Decoder for a Communication Platform. 1-6
  
• Keith Gowan, Jason Nery, Henrick Han, Tony Sheng, Howard Li, Fakhreddine Karray, Insop Song:
  Intelligent Parking System Design Using FPGA. 1-6
  
• Luis F. Rodriguez-Ramos, Angel Alonso, Fernando Gago, Jose V. Gigante, Guillermo Herrera, Teodora Viera:
  Adaptive Optics Real-Time Control Using FPGA. 1-6
  
• Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
  Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. 1-6
  
• Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
  Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. 1-6
  
• Pongstorn Maidee, Kia Bazargan:
  Defect-Tolerant FPGA Architecture Exploration. 1-6
  
• Zhi Guo, Abhishek Mitra, Walid A. Najjar:
  Automation of IP Core Interface Generation for Reconfigurable Computing. 1-6
  
• Daniel Ziener, Stefan Assmus, Jürgen Teich:
  Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. 1-6
  
• Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse:
  IPP Watermarking Technique for IP Core Protection on FPL Devices. 1-6
  
• Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen:
  Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA. 1-6
  
• Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin:
  FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. 1-6
  
• Jean-Baptiste Note, Mark Shand, Jean Vuillemin:
  Real-Time Video Pixel Matching. 1-6
  
• Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert:
  Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs. 1-6
  
• Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
  A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. 1-6
  
• Janina A. Brenner, Jan van der Veen, Sándor P. Fekete, Julio A. de Oliveira Filho, Wolfgang Rosenstiel:
  Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures. 1-6
  
• Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich:
  Minimizing Communication Cost for Reconfigurable Slot Modules. 1-6
  
• Klaus Danne, Roland Mühlenbernd, Marco Platzner:
  Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions. 1-6
  
• Boris Kettelhoit, Mario Porrmann:
  A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. 1-6
  
• Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk:
  Efficient Realtime FPGA Implementation of the Trace Transform. 1-6
  
• Dang Ba Khac Trieu, Tsutomu Maruyama:
  Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA. 1-6
  
• Takashi Saegusa, Tsutomu Maruyama:
  An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree. 1-6
  
• Hideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura:
  A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. 1-6
  
• Andrea Lodi, Claudio Mucci, Massimo Bocchi, Andrea Cappelli, Mario de Dominicis, Luca Ciccarelli:
  A Multi-Context Pipelined Array for Embedded Systems. 1-8
  
• Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
  Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. 1-8
  
• Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou:
  Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. 1-6
  
• Love Singhal, Elaheh Bozorgzadeh:
  Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. 1-8
  
• Allan Carroll, Carl Ebeling:
  Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. 1-6
  
• Thomas Perschke:
  A Flexible Implementation of a Temporal Filter with Motion Compensation. 1-4
  
• Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera:
  A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. 1-4
  
• Christos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff:
  A Dynamic Reconfigurable Fabric for Platform SoCs. 1-4
  
• Fernando Pardo, P. López, Diego Cabello, M. Balsi:
  FPGA Implementation of 3-D Thermal Model Simulator. 1-4
  
• Yohei Hori, Hiroyuki Yokoyama, Kenji Toda:
  Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration. 1-4
  
• Antonin Hermanek, Michal Kunes, Michal Kvasnicka:
  Using Reconfigurable HW for High Dimensional CAF Computation. 1-4
  
• Angel Quiros-Olozabal, Ma de los Angeles Cifredo Chacon, Diego Gomez Vela:
  FPGA-Based Boundary-Scan Bist. 1-4
  
• Koen Van Renterghem, Dieter Verhulst, S. Verschuere, P. Demuytere, Jan Vandewege, Xing-Zhi Qiu:
  A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access. 1-4
  
• Joachim Becker, Yiannos Manoli:
  Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm. 1-4
  
• Xin Wang, Tapani Ahonen, Jari Nurmi:
  Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. 1-6
  
• Julio C. Sosa, Rocío Gómez-Fabela, Jose Antonio Boluda, Fernando Pardo:
  FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow Computation. 1-4
  
• Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede:
  Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers. 1-4
  
• Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata:
  Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. 1-4
  
• Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
  High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. 1-4
  
• Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein:
  From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. 1-4
  
• Yue Zhuo, Hao Li, Saraju P. Mohanty:
  A Congestion Driven Placement Algorithm for FPGA Synthesis. 1-4
  
• Miwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri:
  An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor. 1-4
  
• María José Moure, María Dolores Valdés, Pablo Rodiz, Loreto Rodríguez-Pardo, José Fariña Rodríguez:
  An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution. 1-4
  
• María del Carmen Pérez, Jesús Ureña, Álvaro Hernández, Carlos De Marziani, A. Ochoa, William P. Marnane:
  FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences. 1-4
  
• Carsten Bieser, Martin Bahlinger, Matthias Heinz, Christian Stops, Klaus D. Müller-Glaser:
  A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup. 1-4
  
• Sajid Baloch, Tughrul Arslan, Adrian Stoica:
  An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. 1-4
  
• Oliver Sims, James Irvine:
  An FPGA Implementation of Pattern-Selective Pyramidal Image Fusion. 1-4
  
• Sutjipto Arifin, Peter Y. K. Cheung:
  Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. 1-4
  
• Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly:
  Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. 1-4
  
• F. Javier Toledo, José-Javier Martínez, F. Javier Garrigós, José M. Ferrández, V. Rodellar:
  Skin Color Detection for Real Time Mobile Applications. 1-4
  
• David Grant, Scott Chin, Guy G. Lemieux:
  Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. 1-4
  
• Ignacio Bravo, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Alfredo Gardel:
  Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem. 1-4
  
• Pedro C. Diniz, Gokul Govindu:
  Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit. 1-4
  
• Mário P. Véstias, Horácio C. Neto:
  A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. 1-4
  
• Zhi Guo, Walid A. Najjar:
  A Compiler Intermediate Representation for Reconfigurable Fabrics. 1-4
  
• Mohamed Taher, Tarek A. El-Ghazawi:
  A Segmentation Model for Partial Run-Time Reconfiguration. 1-4
  
• Piotr Stepien, Milan Vasilko:
  On Feasibility of FPGA Bitstream Compression During Placement and Routing. 1-4
  
• Tom Van Court, Martin C. Herbordt:
  Sizing of Processing Arrays for FPGA-Based Computation. 1-6
  
• James Moscola, Young H. Cho, John W. Lockwood:
  Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices. 1-4
  
• Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós:
  Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. 1-4
  
• Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams:
  Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. 1-4
  
• Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki:
  Astra: An Advanced Space-Time Reconfigurable Architecture. 1-4
  
• Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Ivan Gonzalez:
  Self-Reconfigurable Pervasive Platform for Cryptographic Application. 1-4
  
• Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani:
  A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. 1-4
  
• Huang-Chun Roan, Wen-Jyi Hwang, Chia-Tien Dan Lo:
  Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching. 1-6
  
• François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater:
  FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks. 1-4
  
• Balasubramanian Sethuraman, Ranga Vemuri:
  Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. 1-4
  
• Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi:
  A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection. 1-4
  
• Elias Todorovich, Eduardo I. Boemo:
  A-B Nodes Classification for Power Estimation. 1-6
  
• Cesar Torres-Huitzil:
  Area-Efficient Implementation of a Pulse-Mode Neuron Model. 1-4
  
• Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas:
  Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. 1-4
  
• Kostas Siozios, Dimitrios Soudris:
  Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. 1-4
  
• Abdelelah Naoulou, Jean-Louis Boizard, Jean-Yves Fourniols, Michel Devy:
  An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms. 1-4
  
• Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe:
  DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. 1-4
  
• Antonio Martínez, Leonardo Maria Reyneri, Francisco J. Pelayo, Christian A. Morillas, Samuel F. Romero:
  A Codesign Tool for High Level Systhesis of Vision Models on FPL. 1-4
  
• Heikki Kariniemi, Jari Nurmi:
  On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips. 1-6
  
• Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina:
  FPGA Implementation of High-Performance PHM / DPHM Schedulers. 1-4
  
• Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
  Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. 1-6
  
• Paul Saunders, Anthony D. Fagan:
  A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes. 1-6
  
• Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes:
  Reconfigurable Systems Enabled by a Network-on-Chip. 1-4
  
• Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson:
  Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture. 1-4
  
• Timothy F. Oliver, Douglas L. Maskell:
  Execution Objects for Dynamically Reconfigurable FPGA Systems. 1-4
  
• Christoforos Kachris, Stamatis Vassiliadis:
  A Dynamically Reconfigurable Queue Scheduler. 1-4
  
• Martin Novotný, Jan Schmidt:
  General Digit Width Normal Basis Multipliers with Circular and Linear Structure. 1-4
  
• Gustavo Martinez, Jesus Marin, Carlos Willmott:
  FPGA Based Imaging Particle Detector Trigger System. 1-4
  
• Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes:
  A Leak Resistant Architecture Against Side Channel Attacks. 1-4
  
• Wesley Peck, Erik K. Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David L. Andrews:
  Hthreads: A Computational Model for Reconfigurable Devices. 1-4
  
• Mustafa Gök, Çaglar Yilmaz:
  Efficient Cell Designs for Systolic Smith-Waterman Implementations. 1-4
  
• Shrutisagar Chandrasekaran, Abbes Amira:
  FPGA Implementation and Power Modelling of the Fast Walsh Transform. 1-4
  
• Martin J. Pearson, Mokhtar Nibouche, Anthony G. Pipe, Chris Melhuish, Ian Gilhespy, Benjamin Mitchinson, Kevin N. Gurney, Tony J. Prescott, Peter Redgrave:
  A Biologically Inspired FPGA Based Implementation of a Tactile Sensory System for Object Recognition and Texture Discrimination. 1-4
  
• Kyprianos Papademetriou, Apostolos Dollas:
  Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors. 1-4
  
• Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez:
  High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures. 1-4
  
• Jason D. Bakos, Charles L. Cathey, Allen Michalski:
  Predictive Load Balancing for Interconnected FPGAs. 1-4
  
• Cao Zhang, Duncan A. Buell, Allen Michalski:
  The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer. 1-4
  
• Minoru Watanabe, Fuminori Kobayashi:
  A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. 1-6
  
• Balasubramanian Sethuraman:
  Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. 1-2
  
• Thilo Streichert:
  Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks. 1-2
  
• Suhaib A. Fahmy:
  Investigating Trace Transform Architectures for Face Authentication. 1-2
  
• Carlos Morra:
  Configware Design Space Exploration Using Rewriting Logic. 1-2
  
• Su-Shin Ang, George A. Constantinides:
  Dynamic Memory Sub-System for Reconfigurable Platforms. 1-2
  
• Carsten Bieser:
  A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment. 1-2
  
• Tobias Oppold:
  Evaluation and Design of Processor-Like Reconfigurable Architectures. 1-2
  
• Arfan Ghani, T. Martin McGinnity, Liam P. Maguire, Jim Harkin:
  Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware. 1-2
  
• Jonathan A. Clarke, George A. Constantinides:
  High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. 1-2
  
• Elena Perez Ramo, Javier Resano:
  A Dual Cache for Performance and Energy Aware Reconfigurable HW. 1-2
  
• Marco D. Santambrogio, Donatella Sciuto:
  Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign. 1-2
  
• Ben Cope:
  Can Graphics Processing Units be Used to Improve Video Processing Systems? 1-2
  
• Julien Lamoureux, Steven J. E. Wilton:
  Architecture and CAD for FPGA Clock Networks. 1-2
  
• Francisco-Javier Veredas, Hans-Jörg Pfleiderer:
  Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. 1-2
  
• María Brox, Santiago Sánchez-Solano:
  Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs. 1-2
  
• Vinay Sriram, David Kearney:
  High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing. 1-2
  
• Luciano Volcan Agostini, Sergio Bampi:
  FPGA Based Architectures for H. 264/AVC Video Compression Standard. 1-2
  
• Somsubhra Mondal, Seda Ogrenci Memik:
  Power Optimization Techniques for SRAM-Based FPGAs. 1-2
  
• Shrutisagar Chandrasekaran, Abbes Amira:
  Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling. 1-2
  
• Mateusz Majer:
  An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization. 1-2
  
• Pil Woo Chun, Lev Kirischian:
  A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment. 1-2
  

Last update Wed Feb 15 04:06:03 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page