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Publication search results
found 183 matches
- 2006
- Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin:
FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. FPL 2006: 1-6 - Luciano Volcan Agostini, Sergio Bampi:
FPGA Based Architectures for H. 264/AVC Video Compression Standard. FPL 2006: 1-2 - Imran Ahmed, Tughrul Arslan:
A Reconfigurable Viterbi Decoder for a Communication Platform. FPL 2006: 1-6 - Peter Alfke:
Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications. FPL 2006: 1 - Fernando J. Álvarez, Álvaro Hernández, Jesús Ureña, Juan Jesús García, Ana Jiménez, P. Santa Teresa:
Detection Module in a Complementary Set of Sequences-Based Pulse Compression System. FPL 2006: 1-6 - Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura:
A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. FPL 2006: 1-6 - David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
Fast Emulation of Permanent Faults in VLSI Systems. FPL 2006: 1-6 - Su-Shin Ang, George A. Constantinides:
Dynamic Memory Sub-System for Reconfigurable Platforms. FPL 2006: 1-2 - Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez:
High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures. FPL 2006: 1-4 - Sutjipto Arifin, Peter Y. K. Cheung:
Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. FPL 2006: 1-4 - Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jung:
Regular Expression Software Deceleration for Intrusion Detection Systems. FPL 2006: 1-8 - Jason D. Bakos, Charles L. Cathey, Allen Michalski:
Predictive Load Balancing for Interconnected FPGAs. FPL 2006: 1-4 - Sajid Baloch, Tughrul Arslan, Adrian Stoica:
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. FPL 2006: 1-4 - Nastaran Baradaran, Pedro C. Diniz:
Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures. FPL 2006: 1-6 - Luis G. Barbero, John S. Thompson:
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems. FPL 2006: 1-6 - Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede:
Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers. FPL 2006: 1-4 - Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert:
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs. FPL 2006: 1-6 - Joachim Becker, Yiannos Manoli:
Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm. FPL 2006: 1-4 - Carsten Bieser:
A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment. FPL 2006: 1-2 - Carsten Bieser, Martin Bahlinger, Matthias Heinz, Christian Stops, Klaus D. Müller-Glaser:
A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup. FPL 2006: 1-4 - Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping Li:
FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. FPL 2006: 1-6 - Ignacio Bravo Muñoz, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Alfredo Gardel Vicente:
Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem. FPL 2006: 1-4 - Janina A. Brenner, Jan van der Veen, Sándor P. Fekete, Julio A. de Oliveira Filho, Wolfgang Rosenstiel:
Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures. FPL 2006: 1-6 - María Brox, Santiago Sánchez-Solano:
Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs. FPL 2006: 1-2 - Oswaldo Cadenas, Graham M. Megson:
Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor. FPL 2006: 1-6 - Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL 2006: 1-4 - Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon:
High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD. FPL 2006: 1-6 - Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6 - Allan Carroll, Carl Ebeling:
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. FPL 2006: 1-6 - Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse:
IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL 2006: 1-6
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