• 
  Antonio Núñez, Pedro P. Carballo (Eds.): 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece. IEEE Computer Society 2009 ISBN 978-0-7695-3782-5

Systems-on-a-Chip and MultiProcessor SoCs (1)

• 
  Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid: A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. 3-10
• 
  Shadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, Andreas Herkersdorf: An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. 11-18
• 
  Yoshiyasu Ogasawara, Hironori Nakajo: An Effective Replacement Strategy of Cache Memory for an SMT Processor. 19-25
• 
  Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas: An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload. 26-33

System Synthesis (1)

• 
  Marcel Steine, Marco Bekooij, Maarten Wiggers: A Priority-Based Budget Scheduler with Conservative Dataflow Model. 37-44
• 
  Alexandru Amaricai, Oana Boncalo: Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation. 45-49
• 
  Adam Pawlak, Piotr Penkala, Pawel Fras, Wojciech Sakowski, Gunter Grau, Szymon Grzybek, Alexander Stanitzki: Distributed Collaborative Design of a Mixed-Signal IP Component. 50-57

Circuit Design (1)

• 
  Mohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi: A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling. 61-66
• 
  Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi: Improving Latency of Quantum Circuits by Gate Exchanging. 67-73
• 
  Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto: Run-Time Reconfigurable Array Using Magnetic RAM. 74-81

Fault Tolerance in Digital System Design (1)

• 
  Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: Robustness Check for Multiple Faults Using Formal Techniques. 85-90
• 
  Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxiras: Instruction Precomputation for Fault Detection. 91-99
• 
  Werner Friesenbichler, Andreas Steininger: Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. 100-107
• 
  Martin Straka, Zdenek Kotásek: High Availability Fault Tolerant Architectures Implemented into FPGAs. 108-115

Systems-on-a-Chip and MultiProcessor SoCs (2)

• 
  Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania: Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. 119-126
• 
  Li Tong, Zhonghai Lu, Hua Zhang: Exploration of Slot Allocation for On-Chip TDM Virtual Circuits. 127-132
• 
  Amit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan: Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms. 133-140
• 
  Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen: Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks. 141-146

System Synthesis (2)

• 
  Sven Rosinger, Kiril Schröder, Wolfgang Nebel: Power Management Aware Low Leakage Behavioural Synthesis. 149-156
• 
  Ioannis Kouretas, Vassilis Paliouras: Variation-tolerant Design Using Residue Number System. 157-163
• 
  George Economakos, Sotirios Xydis: Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. 164-171
• 
  Evangelos Vassalos, Dimitris Bakalis: Combined SD-RNS Constant Multiplication. 172-179

Circuit Design (2)

• 
  Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simunic Rosing: Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. 183-190
• 
  Nikos Petrellis, Michael K. Birbas, John C. Kikidis, Alexios N. Birbas: Calibration Method for a CMOS 0.06mm² 150MS/s 8-bit ADC. 191-195
• 
  Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi, Javier Sosa, Héctor Navarro: Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications. 196-199

Poster Introduction / Poster Session (1)

• 
  Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen: An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs. 203-206
• 
  Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser: Model-Driven Design of Embedded Multimedia Applications on SoCs. 207-210
• 
  Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França: GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. 211-216
• 
  Eric Senn, David Monnereau, André Rossi, Nathalie Julien: Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors. 217-220
• 
  Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus: Reliability Estimation Process. 221-224
• 
  Franco Fummi, Davide Quaglia, Francesco Stefanni: Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems. 225-228
• 
  Raimund Ubar, Sergei Kostin, Jaan Raik: Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. 229-232
• 
  Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera: High Performance Image Processing on a Massively Parallel Processor Array. 233-236

Systems-on-a-Chip and MultiProcessor SoCs (3)

• 
  Zhiyuan He, Zebo Peng, Petru Eles: Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment. 239-246
• 
  Meysam Taassori, Shaahin Hessabi: Low Power Encoding in NoCs Based on Coupling Transition Avoidance. 247-254
• 
  Andreas Lankes, Thomas Wild, Andreas Herkersdorf: Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. 255-262
• 
  Mengxiao Liu, Weixing Ji, Jiaxin Li, Xing Pu: Storage Architecture for an On-chip Multi-core Processor. 263-270

Synthesis of Arithmetic Circuits

• 
  Rui Duarte, Horácio C. Neto, Mário P. Véstias: Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. 273-280
• 
  Feng Liu, Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed, Gang Chen, Xiaoyu Song, QingPing Tan: A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC. 281-286
• 
  Marco Gerards, Jan Kuper, André B. J. Kokkeler, Bert Molenkamp: Streaming Reduction Circuit. 287-292
• 
  Daniel Piso Fernandez, Javier D. Bruguera: Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. 293-300

Circuit Design (3)

• 
  Simon Hollis: Pulse Generation for On-chip Data Transmission. 303-310
• 
  Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi: High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output. 311-314
• 
  Andrea Ricci, Ilaria De Munari, Paolo Ciampolini: Performance-Effective Compaction of Standard-Cell Libraries for Digital Design. 315-322

Fault Tolerance in Digital System Design (2)

• 
  Peter Tummeltshammer, Andreas Steininger: On the Risk of Fault Coupling over the Chip Substrate. 325-332
• 
  Makoto Sugihara: Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints. 333-340
• 
  Jimmy Tarrillo, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas: A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems. 341-347
• 
  Jaroslav Borecky, Pavel Kubalík, Hana Kubatova: Reliable Railway Station System Based on Regular Structure Implemented in FPGA. 348-354
• 
  Richard Ruzicka: Dependable Controller Design Using Polymorphic Counters. 355-362

Systems-on-a-Chip and MultiProcessor SoCs (4)

• 
  Kees Goossens, Lotfi Mhamdi, Iria Varela Senin: Internet-Router Buffered Crossbars Based on Networks on Chip. 365-374
• 
  Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel: Network-on-Chip Architecture Exploration Framework. 375-382
• 
  Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria: Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip. 383-389
• 
  Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot: Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study. 390-397

System-Level Energy Optimization of HW/SW Embedded Systems

• 
  Ahmed Mohamed AbdelHamid, Ankur Anchlia, Stylianos Mamagkakis, Miguel Corbalan Miranda, Bart Dierickx, Maarten Kuijk: A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning. 401-408
• 
  Anca Mariana Molnos, Kees Goossens: Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors. 409-418
• 
  Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris: Compilation Technique for Loop Overhead Minimization. 419-426
• 
  Ming-Yan Yu, Ming Li, Jun-Jie Song, Fang-Fa Fu, Yu-Xin Bai: Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip. 427-432

Flexible Digital Radio (1)

• 
  Dominique Nussbaum, Karim Khalfallah, Christophe Moy, Amor Nafkha, Pierre Leray, Julien Delorme, Jacques Palicot, Jérôme Martin, Fabien Clermidy, Bertrand Mercier, Renaud Pacalet: Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques. 435-440
• 
  Panayiotis Savvopoulos, Nikolaos Papandreou, Theodore Antonakopoulos: Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator. 441-448
• 
  Fabien Clermidy, Romain Lemaire, Xavier Popon, Dimitri Ktenas, Yvain Thonnart: An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application. 449-456

Fault Tolerance, Dependability and Testing

• 
  Roland Dobai, Elena Gramatová: Deductive Fault Simulation for Asynchronous Sequential Circuits. 459-464
• 
  Michael Birner, Thomas Handl: ARROW - A Generic Hardware Fault Injection Tool for NoCs. 465-472
• 
  Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani, Mahmood Fathy, Reza Berangi: A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. 473-480
• 
  Oana Boncalo, Alexandru Amaricai: Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation. 481-487
• 
  David Guzman, Manuel Prieto, Daniel Garcia, Victor Ruiz, Javier Almena, Sebastian Sanchez, Daniel Meziat: High Reliable Remote Terminal Unit for Space Applications. 488-493

Processor and System Synthesis (1)

• 
  Asadollah Shahbahrami, Ben H. H. Juurlink: SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform. 497-504
• 
  Zheng Shen, Hu He, Yihe Sun: Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. 505-512
• 
  Minwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, Yunheung Paek: Iterative Algorithm for Compound Instruction Selection with Register Coalescing. 513-520
• 
  Robert Czerwinski, Dariusz Kania: CPLD-oriented Synthesis of Finite State Machines. 521-528

System Synthesis (3)

• 
  Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, François Charot: Architecture-Driven Synthesis of Reconfigurable Cells. 531-538
• 
  Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick: An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication. 539-546
• 
  Benny Akesson, Andreas Hansson, Kees Goossens: Composable Resource Sharing Based on Latency-Rate Servers. 547-555

Flexible Digital Radio (2)

• 
  Damien Hedde, Pierre-Henri Horrein, Frédéric Pétrot, Robin Rolland, Franck Rousseau: A MPSoC Prototyping Platform for Flexible Radio Applications. 559-566
• 
  Amin El Mrabti, Hamed Sheibanyrad, Frédéric Rousseau, Frédéric Pétrot, Romain Lemaire, Jérôme Martin: Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation. 567-574
• 
  Maroun Ojail, Raphaël David, Stéphane Chevobbe, Didier Demigny: Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems. 575-581
• 
  Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel: Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. 582-589

Poster Introduction / Poster Session (2)

• 
  Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi: High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic. 593-596
• 
  Joris Borms, Kris Steenhaut, Bart Lemmens, Ann Nowé: Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks. 597-600
• 
  Jan Schmidt, Petr Fiser: The Case for a Balanced Decomposition Process. 601-604
• 
  Petr Mikusek, Václav Dvorák: Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization. 605-608
• 
  Thomas Tsiolakis, Nikos Konofaos, George Alexiou: Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder. 609-612
• 
  Marius Gligor, Nicolas Fournel, Frédéric Pétrot: Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture. 613-616
• 
  Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee: Survey of Test Data Compression Technique Emphasizing Code Based Schemes. 617-620
• 
  Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit: A Concept for Logic Self Repair. 621-624

Processor and System Synthesis (2)

• 
  Luis A. Tarazona, Doug A. Edwards, Luis A. Plana: A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. 627-634
• 
  Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López, José Duato: An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. 635-642
• 
  Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales: An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. 643-650
• 
  Sandro Penolazzi, Luca Bolognino, Ahmed Hemani: Energy and Performance Model of a SPARC Leon3 Processor. 651-656

Programmable/Re-Configurable Architectures (1)

• 
  Lu Gao, Li Guo, Canxing Lu: Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers. 659-666
• 
  Arturo Diaz-Perez, Mario Alberto Garcia Martinez: FPGA Accelerator for RNA Secondary Structure Prediction. 667-671
• 
  Giovanni Danese, Mauro Giachero, Francesco Leporati, Giulia Matrone, Nelson Nazzicari: An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm. 672-679
• 
  Julien Lallet, Sébastien Pillement, Olivier Sentieys: xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. 680-687

Applications of (Embedded) Digital Systems (1)

• 
  Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu: A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation. 691-698
• 
  Rizwan Asghar, Di Wu, Johan Eilert, Dake Liu: Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. 699-706
• 
  Vaclav Simek, Radim Dvorak, Frantisek Zboril, Vladimír Drábek: GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations. 707-713
• 
  Ozgur Tasdizen, Ilker Hamzaoglu: A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video. 714-719

Dependability and Testing of Digital Systems

• 
  Antonio da Silva, Sebastián Sánchez: Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models. 723-728
• 
  Xiao Zhang, Hans G. Kerkhoff: Design of a Highly Dependable Beamforming Chip. 729-735
• 
  Apostolos P. Fournaris, Odysseas G. Koufopavlou: One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm. 736-741
• 
  Raj Kumar Nagpal, Rakesh Malik, Jai Narayan Tripathi: Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links. 742-745

Logic Synthesis

• 
  D. Michael Miller, Robert Wille, Gerhard W. Dueck: Synthesizing Reversible Circuits for Irreversible Functions. 749-756
• 
  Petr Fiser, David Toman: A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. 757-764
• 
  Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura: Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. 765-772
• 
  Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa: Logic Minimization and Testability of 2SPP-P-Circuits. 773-780

Programmable/Re-Configurable Architectures (2)

• 
  Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane: FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash. 783-790
• 
  George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu: Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. 791-798
• 
  Mario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda, Michel Devy, Jean-Louis Boizard, Jean-Yves Fourniols: Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization. 799-805

Applications of (Embedded) Digital Systems (2)

• 
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: The Parallel Sieve Method for a Virus Scanning Engine. 809-816
• 
  Hamid Reza Ahmadi, Ali Afzali-Kusha: Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm. 817-822
• 
  Jan Kastil, Jan Korenek, Ondrej Lengál: Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. 823-829

Wireless Sensor Networks

• 
  José Carlos Alves, Nuno Alexandre Cruz: An FPGA-Based Embedded System for a Sailing Robot. 830-837
• 
  Perfecto Mariño Espiñeira, Fernando Pérez-Fontán, Miguel Angel Domínguez, Santiago Otero: Ad-hoc WSN in Biological Research. 841-848
• 
  James Mathews, Matthew Barnes, D. K. Arvind: Low Power Free Space Optical Communication in Wireless Sensor Networks. 849-856
• 
  Carlo Brandolese, William Fornaciari: A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes. 857-864
• 
  Milan Nenad Simic, Randeep Singh, Louis Doukas, Aliakbar Akbarzadeh: Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds. 865-869