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ORCIDJean-Luc Dekeyser
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- affiliation: LIFL, Lille, France
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2010 – 2019
- 2019
[j32]Karim M. A. Ali
, Rabie Ben Atitallah, Abdessamad Ait El Cadi, Nizar Fakhfakh, Jean-Luc Dekeyser:
ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. Int. J. Reconfigurable Comput. 2019: 4298013:1-4298013:19 (2019)- [j31]Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
SCAC: Weakly-coupled execution model for massively parallel systems. Microprocess. Microsystems 64: 128-142 (2019) - 2018
- [j30]Gilberto Ochoa-Ruiz, Pamela Wattebled, Maamar Touiza, Florent de Lamotte, El-Bay Bourennane, Samy Meftali, Jean-Luc Dekeyser, Jean-Philippe Diguet:
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. J. Parallel Distributed Comput. 112: 1-19 (2018) - [j29]Rabie Ben Atitallah, Venkatasubramanian Viswanathan, Nicolas Bélanger, Jean-Luc Dekeyser:
FPGA-Centric Design Process for Avionic Simulation and Test. IEEE Trans. Aerosp. Electron. Syst. 54(3): 1047-1065 (2018) - 2017
- [c101]Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser:
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. ARC 2017: 168-176 - 2016
- [c100]Wissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser:
AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture. MCSoC 2016: 1-7 - [c99]Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. PDP 2016: 759-762 - 2015
- [j28]Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
FPGA-based many-core System-on-Chip design. Microprocess. Microsystems 39(4-5): 302-312 (2015) - [j27]Vincent Aranega, Jean-Marie Mottu, Anne Etien, Thomas Degueule, Benoit Baudry, Jean-Luc Dekeyser:
Towards an automation of the mutation analysis dedicated to model transformation. Softw. Test. Verification Reliab. 25(5-7): 653-683 (2015) - [c98]Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System. FCCM 2015: 165 - [c97]Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache:
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). FPGA 2015: 266 - [c96]Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser:
Using hardware parallelism for reducing power consumption in video streaming applications. ReCoSoC 2015: 1-7 - [c95]Jean-Luc Dekeyser, A. Shadi Aljendi:
Adopting new learning strategies for computer architecture in higher education: case study: building the S3 microprocessor in 24 hours. WCAE 2015: 6:1-6:8 - 2014
- [j26]Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser:
Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design. Knowl. Eng. Rev. 29(4): 433-451 (2014) - [c94]Chiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Model-driven design flow for distributed control in reconfigurable FPGA systems. DASIP 2014: 1-6 - [c93]Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache:
Redefining the role of FPGAs in the next generation avionic systems (abstract only). FPGA 2014: 248 - [c92]Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser:
A generic pixel distribution architecture for parallel video processing. ReConFig 2014: 1-8 - [c91]Mokhtar Bouain, Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Communication-centric design for FMC based I/O system. ReCoSoC 2014: 1-8 - 2013
- [j25]Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser:
An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL. Comput. Sci. Eng. 15(1): 46-55 (2013) - [j24]Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. Integr. 46(4): 404-412 (2013) - [j23]Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Decentralized control for dynamically reconfigurable FPGA systems. Microprocess. Microsystems 37(8-A): 871-884 (2013) - [c90]Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Master-Slave Control Structure for Massively Parallel System on Chip. DSD 2013: 917-924 - 2012
- [j22]Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
System level modeling methodology of NoC design from UML-MARTE to VHDL. Des. Autom. Embed. Syst. 16(4): 161-187 (2012) - [j21]Adolf Samir Abdallah, Abdoulaye Gamatié, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Abstract Clock-Based Design of a JPEG Encoder. IEEE Embed. Syst. Lett. 4(2): 29-32 (2012) - [j20]Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser:
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives. J. Syst. Archit. 58(5): 178-194 (2012) - [j19]Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser:
A fast MPSoC virtual prototyping for intensive signal processing applications. Microprocess. Microsystems 36(3): 176-189 (2012) - [c89]Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Semi-distributed Control for FPGA-based Reconfigurable Systems. DSD 2012: 185-192 - [c88]Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Eric Senn, Smaïl Niar:
An efficient power estimation methodology for complex RISC processor-based platforms. ACM Great Lakes Symposium on VLSI 2012: 239-244 - [c87]Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Broadcast with mask on a massively parallel processing on a chip. HPCS 2012: 275-280 - [c86]Gilberto Ochoa-Ruiz, Ouassila Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser:
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. ReConFig 2012: 1-8 - [c85]Venkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean-Luc Dekeyser:
Dynamic reconfiguration of modular I/O IP cores for avionic applications. ReConFig 2012: 1-6 - [c84]Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Distributed control for reconfigurable FPGA systems: A high-level design approach. ReCoSoC 2012: 1-8 - [c83]Pamela Wattebled, Jean-Philippe Diguet, Jean-Luc Dekeyser:
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems. ReCoSoC 2012: 1-8 - [c82]Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser:
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. RSP 2012: 107-113 - 2011
- [j18]Vincent Aranega, Anne Etien, Jean-Luc Dekeyser:
Using an Alternative Trace for QVT. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 42 (2011) - [j17]Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser, Abderrazek Jemai:
A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. EURASIP J. Embed. Syst. 2011 (2011) - [j16]Yassine Aydi, Mouna Baklouti, Mohamed Abid, Jean-Luc Dekeyser:
A multi-level design methodology of multistage interconnection network for MPSOCs. Int. J. Comput. Appl. Technol. 42(2/3): 191-203 (2011) - [j15]Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Rabie Ben Atitallah, Anne Etien, Philippe Marquet, Jean-Luc Dekeyser:
A Model-Driven Design Framework for Massively Parallel Embedded Systems. ACM Trans. Embed. Comput. Syst. 10(4): 39:1-39:36 (2011) - [j14]Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser:
Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture. Tech. Sci. Informatiques 30(9): 1089-1113 (2011) - [c81]George Afonso, Rabie Ben Atitallah, Nicolas Bélanger, Martial Rubio, Stephan Stilkerich, Jean-Luc Dekeyser:
Toward generic and adaptive avionic test systems. AHS 2011: 287-294 - [c80]Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser:
Fast and accurate hybrid power estimation methodology for embedded systems. DASIP 2011: 45-51 - [c79]Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser:
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. DASIP 2011: 269-276 - [c78]Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. DASIP 2011: 308-315 - [c77]Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser:
Hybrid system level power consumption estimation for FPGA-based MPSoC. ICCD 2011: 239-246 - [c76]Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser:
A system level power consumption estimation for MPSoC. SoC 2011: 56-61 - [c75]George Afonso, Rabie Ben Atitallah, Alexander Loyer, Jean-Luc Dekeyser, Nicolas Bélanger, Martial Rubio:
A prototyping environment for high performance reconfigurable computing. ReCoSoC 2011: 1-8 - [c74]Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser:
A model-driven based framework for rapid parallel SoC FPGA prototyping. International Symposium on Rapid System Prototyping 2011: 149-155 - [i4]Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser:
Programming Massively Parallel Architectures using MARTE: a Case Study. CoRR abs/1103.4881 (2011) - [i3]Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser:
A Modeling Approach based on UML/MARTE for GPU Architecture. CoRR abs/1105.4424 (2011) - [i2]Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser, Yvonnick Le Menach:
Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines. CoRR abs/1107.0538 (2011) - 2010
- [j13]Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser:
Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. Int. J. Embed. Syst. 4(3/4): 204-224 (2010) - [j12]Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA. J. Syst. Archit. 56(7): 278-292 (2010) - [c73]Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. ARC 2010: 110-121 - [c72]Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. DASIP 2010: 68-75 - [c71]Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. DSD 2010: 706-713 - [c70]Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
IP Based Configurable SIMD Massively Parallel SoC. FPL 2010: 247-250 - [c69]Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser:
Correct and energy-efficient design of SoCs: The H.264 encoder case study. SoC 2010: 115-120 - [c68]Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. ISSPIT 2010: 528-531 - [c67]Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser:
Traceability for Mutation Analysis in Model Transformation. MoDELS (Workshops) 2010: 259-273 - [i1]Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Yvonnick Le Menach, Jean-Luc Dekeyser:
Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines. CoRR abs/1010.4639 (2010)
2000 – 2009
- 2009
- [j11]Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
High level modeling of Dynamic Reconfigurable FPGAs. Int. J. Reconfigurable Comput. 2009: 408605:1-408605:15 (2009) - [j10]Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser:
Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. Scalable Comput. Pract. Exp. 10(2) (2009) - [c66]Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. AICCSA 2009: 368-373 - [c65]Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid:
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. DSD 2009: 3-10 - [c64]Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser:
Model-Driven Design of Embedded Multimedia Applications on SoCs. DSD 2009: 207-210 - [c63]Yassine Aydi, Ramzi Tligue, Maissa Elleuch, Mohamed Abid, Jean-Luc Dekeyser:
A multi level functional verification of multistage interconnection network for MPSOC. ICECS 2009: 439-442 - [c62]Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser:
Traceability Mechanism for Error Localization in Model Transformation. ICSOFT (1) 2009: 66-73 - [c61]Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser:
Using Trace to Situate Errors in Model Transformations. ICSOFT (Selected Papers) 2009: 137-149 - 2008
- [j9]Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser:
Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP J. Embed. Syst. 2008 (2008) - [j8]Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser:
Safe design of high-performance embedded systems in an MDE framework. Innov. Syst. Softw. Eng. 4(3): 215-222 (2008) - [c60]Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser:
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. ASAP 2008: 126-131 - [c59]Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. ESTIMedia 2008: 47-52 - [c58]Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser:
MARTE-based Design of a Multimedia Application and Formal Analysis. FDL 2008: 160-166 - [c57]Sebastien Revol, Safouan Taha, François Terrier, Alain Clouard, Sébastien Gérard, Ansgar Radermacher, Jean-Luc Dekeyser:
Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. DIPES 2008: 69-78 - [c56]Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser:
Using an MDE Approach for Modeling of Interconnection Networks. ISPAN 2008: 289-294 - [c55]Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser:
Modeling and Formal Validation of High-Performance Embedded Systems. ISPDC 2008: 215-222 - [c54]Julien Taillard, Frédéric Guyomarc'h, Jean-Luc Dekeyser:
A Graphical Framework for High Performance Computing Using An MDE Approach. PDP 2008: 165-173 - 2007
- [c53]Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser:
Massively parallel processing on a chip. Conf. Computing Frontiers 2007: 277-286 - [c52]Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser:
Model Transformations from a Data Parallel Formalism towards Synchronous Languages. FDL 2007: 255-260 - [c51]Safouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser:
MARTE: UML-based Hardware Design from Modelling to Simulation. FDL 2007: 274-279 - [c50]Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
A Design Flow to Map Parallel Applications onto FPGAs. FPL 2007: 605-608 - [c49]Éric Piel, Philippe Marquet, Jean-Luc Dekeyser:
Model Transformations for the Compilation of Multi-processor Systems-on-Chip. GTTSE 2007: 459-473 - [c48]Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
Multiple Abstraction Views of FPGA to Map Parallel Applications. ReCoSoC 2007: 90-97 - [c47]Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser:
An MPSoC Performance Estimation Framework Using Transaction Level Modeling. RTCSA 2007: 525-533 - [c46]Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser:
An Open Framework for Detailed Hardware Modeling. SIES 2007: 118-125 - [c45]Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser:
Multilevel MPSOC simulation using an MDE approach. SoCC 2007: 197-200 - 2006
- [j7]Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson:
A universal performance factor for multi-criteria evaluation of multistage interconnection networks. Future Gener. Comput. Syst. 22(7): 794-804 (2006) - [c44]Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser:
Estimating Energy Consumption for an MPSoC Architectural Exploration. ARCS 2006: 298-310 - [c43]Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser:
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. DSD 2006: 280-287 - [c42]Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Pierre Boulet:
UML2 Profile for Modeling Controlled Data Parallel Applications. FDL 2006: 359-367 - [c41]Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser:
Real-time systems for multiprocessor architectures. IPDPS 2006 - [c40]Rabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser:
Multilevel MPSoC Performance Evaluation Using MDE Approach. SoC 2006: 1-4 - [c39]Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser:
Safe Design Methodology for an Intelligent Cruise Control System with GPS. VTC Fall 2006: 1-5 - 2005
- [c38]J. Vennin, S. Penain, Luc Charest, Samy Meftali, Jean-Luc Dekeyser:
Embed Scripting inside SystemC. FDL 2005: 373-385 - [c37]Lossan Bonde, Pierre Boulet, Jean-Luc Dekeyser:
Traceability and Interoperability in Models Transformations. FDL 2005: 543-555 - [c36]Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet:
Mode-Automata Based Methodology for Scade. HSCC 2005: 386-401 - [c35]Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson:
Scalable Multistage Network for Multiprocessor System-on-Chip Design. ISPAN 2005: 352-357 - [c34]Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser:
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. PPAM 2005: 896-903 - [c33]Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena:
Model Driven Engineering for Regular MPSoC Co-design. ReCoSoC 2005: 129-136 - [c32]Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet:
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. MoDELS 2005: 445-459 - 2004
- [c31]Lossan Bonde, Cédric Dumoulin, Jean-Luc Dekeyser:
Metamodels and MDA Transformations for Embedded Systems. FDL 2004: 240-252 - [c30]Arnaud Cuccuru, Pierre Boulet, Jean-Luc Dekeyser:
Regular Hardware Architecture Modeling with UML2. FDL 2004: 289-301 - [c29]E. Turbatu, Samy Meftali, Smaïl Niar, Jean-Luc Dekeyser:
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). FDL 2004: 378-380 - [c28]M. Samyn, Samy Meftali, Jean-Luc Dekeyser:
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. FDL 2004: 452-463 - [c27]Arnaud Cuccuru, Philippe Marquet, Jean-Luc Dekeyser:
UML2 as an ADL Hierarchichal Hardware Modeling. IFIP-WADL 2004: 133-147 - [c26]Samy Meftali, Jean-Luc Dekeyser:
SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. Virtual Enterprises and Collaborative Networks 2004: 387-394 - [c25]Samy Meftali, Jean-Luc Dekeyser:
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. IWSOC 2004: 55-58 - [c24]Ahmad Chadi Aljundi, Jean-Luc Dekeyser:
The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks. PDP 2004: 72- - 2003
- [c23]Ahmad Chadi Aljundi, Jean-Luc Dekeyser, Isaac D. Scherson:
An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks. PDCS 2003: 1-8 - [c22]Cédric Dumoulin, Jean-Luc Dekeyser, Boris Kokoszko, S. Pulon, G. Cristau:
Interoperability between Design and Simulation Tools using Model Transformation Techniques. FDL 2003: 274-285 - [c21]Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet:
MDA for SoC Design, Intensive Signal Processing Experiment. FDL 2003: 309-317 - [c20]Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson:
A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks. IPDPS 2003: 277 - [c19]Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser, T. Theeuwen:
Distributed Process Networks - Using Half FIFO Queues in CORBA. PARCO 2003: 31-38 - 2002
- [j6]Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser:
Towards Distributed Process Networks with CORBA. Scalable Comput. Pract. Exp. 5(4) (2002) - [c18]Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet:
GASPARD - A Visual Parallel Programming Environment. PARELEC 2002: 145-150 - 2001
- [c17]Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser:
Compilation Principle of a Specification Language Dedicated to Signal Processing. PaCT 2001: 358-370 - [c16]Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, Alain Demeure:
Visual Data-Parallel Programming for Signal Processing Applications. PDP 2001: 105-112 - 2000
- [c15]