23. DAC 1986:
Las Vegas, Nevada, USA
Robert M. Williams:
IBM perspectives on the electrical design automation industry (keynote address).
1
Edward H. Frank:
Exploiting parallelism in a switch-level simulation machine.
20-26
J. M. Hancock,
S. DasGupta:
Tutorial on parallel processing for design automation applications (tutorial session).
69-77
Aart J. de Geus:
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference.
78
Tsutomu Sasao:
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators.
86-93
Sching L. Lin,
Jonathan Allen:
Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layout.
123-130
Dan Adler:
SIMMOS: a multiple-delay switch-level simulator.
159-163
Yue-Sun Kuo,
W. K. Chou:
Generating essential primes for a Boolean function with multiple-valued inputs.
193-199
Ralph Marlett:
An effective test generation system for sequential circuits.
250-256
Peter Marwedel:
A new synthesis for the MIMOLA software system.
271-277
Zebo Peng:
Synthesis of VLSI systems with the CAMAD design aid.
278-284
Mark R. Hartoog:
Analysis of placement procedures for VLSI standard cell layout.
314-319
Moe Shahdad:
An overview of VHDL language and technology.
320-326
John P. Eurich:
A tutorial introduction to the electronic design interchange format (tutorial session).
327-333
Wilfried Daehn:
A unified treatment of PLA faults by Boolean differences.
334-338
Gerd Krüger:
Automatic generation of self-test programs - a new feature of the MIMOLA design system.
378-384
Michael C. McFarland:
Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions.
474-480
Charles H. Ng:
An industrial world channel router for non-rectangular channels.
490-494
Wojciech Maly:
Optimal order of the VLSI IC testing sequence.
560-566
Alan J. Coppola:
An implementation of a state assignment heuristic.
643-649
Sumit Ghosh:
A rule-based approach to unifying functional and fault simulation and timing verification.
677-682
Wayne Wolf:
An object-oriented, procedural database for VLSI chip planning.
744-751
Robert P. Larsen:
Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis.
768-777
Robert E. Canright:
Simulating and controlling the effects of transmission line impedance mismatches.
778-785
Pat Lamey:
Early verification of prototype tooling for IC designs.
819-822
data released under the ODC-BY 1.0 license
