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Publication search results
found 60 matches
- 2002
- Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(1): 5 (2002) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(2): 103-104 (2002) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(3): 255 (2002) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(4-5): 359 (2002) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(6): 567-568 (2002) - Joakim Aidemark, Peter Folkesson, Johan Karlsson:
Path-Based Error Coverage Prediction. J. Electron. Test. 18(3): 343-349 (2002) - Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik:
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. J. Electron. Test. 18(4-5): 475-485 (2002) - Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. J. Electron. Test. 18(4-5): 455-473 (2002) - Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto:
Reliability Properties Assessment at System Level: A Co-Design Framework. J. Electron. Test. 18(3): 351-356 (2002) - Krishnendu Chakrabarty:
Guest Editorial. J. Electron. Test. 18(4-5): 363 (2002) - Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. 18(6): 571-581 (2002) - Li Chen, Xiaoliang Bai, Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. J. Electron. Test. 18(4-5): 529-538 (2002) - Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson:
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. J. Electron. Test. 18(6): 583-594 (2002) - Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electron. Test. 18(1): 17-28 (2002) - Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electron. Test. 18(1): 73-88 (2002) - Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electron. Test. 18(3): 261-271 (2002) - René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. 18(2): 145-157 (2002) - Rainer Dorsch, Hans-Joachim Wunderlich:
Reusing Scan Chains for Test Pattern Decompression. J. Electron. Test. 18(2): 231-240 (2002) - Magnus Eckersand, Fredrik Franzon, Ken Filliter:
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function. J. Electron. Test. 18(2): 171-177 (2002) - Michele Favalli, Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. J. Electron. Test. 18(3): 273-283 (2002) - Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
State and Fault Information for Compaction-Based Test Generation. J. Electron. Test. 18(1): 63-72 (2002) - Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electron. Test. 18(3): 285-294 (2002) - Bruce S. Greene, Samiha Mourad:
Partial Scan Testing on the Register-Transfer Level. J. Electron. Test. 18(6): 613-626 (2002) - Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
On Concurrent Test of Core-Based SOC Design. J. Electron. Test. 18(4-5): 401-414 (2002) - Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy:
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electron. Test. 18(2): 189-201 (2002) - Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electron. Test. 18(1): 55-62 (2002) - André Ivanov:
Test Technology Technical Council Newsletter. J. Electron. Test. 18(2): 105-106 (2002) - André Ivanov:
Test Technology Technical Council Newsletter. J. Electron. Test. 18(3): 257-258 (2002) - André Ivanov:
Test Technology Technical Council Newsletter. J. Electron. Test. 18(4-5): 361-362 (2002) - Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electron. Test. 18(2): 213-230 (2002)
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