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Publication search results
found 67 matches
- 2010
- Ladislav Andricek, Michael Beimforde, Armin Klumpp, Anna Macchiolo, Karl-Reinhard Merkel, Hans-Günther Moser, Richard Nisius, Rainer Helmut Richter, Josef Weber, Philipp Weigell, Robert Wieland:
Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC. 3DIC 2010: 1-4 - Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda:
Wafer-level hybrid bonding technology with copper/polymer co-planarization. 3DIC 2010: 1-4 - Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli:
Performance analysis of 3-D monolithic integrated circuits. 3DIC 2010: 1-4 - Jeff Burns:
3D integration - A server perspective. 3DIC 2010: 1-20 - Yann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne:
A novel concept for ultra-low capacitance via-last TSV. 3DIC 2010: 1-4 - D. Le Cunff, A. Pravdivtsev, K. Le Chao, C. Euvrard, Emilie Deloffre, A. Cailean:
Use of optical metrology for wafer level packaging of CMOS image sensor. 3DIC 2010: 1-6 - Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
CMIT - A novel cluster-based topology for 3D stacked architectures. 3DIC 2010: 1-5 - Grzegorz Deptuch:
3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and Tezzaron. 3DIC 2010: 1-10 - Grzegorz Deptuch, Marcel Demarteau, Jim Hoff, Ronald Lipton, Alpana Shenai, Raymond Yarema, Tom Zimmerman:
Pixel detectors in 3D technologies for high energy physics. 3DIC 2010: 1-4 - Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Design and early evaluation of a 3-D die stacked chip multi-vector processor. 3DIC 2010: 1-8 - Rebha El Farhane, Myriam Assous, Patrick Leduc, Aurélie Thuaire, David Bouchu, Hélène Feldis, Nicolas Sillon:
A successful implementation of dual damascene architecture to copper TSV for 3D high density applications. 3DIC 2010: 1-4 - Montserrat Fernandez-Bolaños, Adrian M. Ionescu:
3D heterogeneous integration for novel functionality. 3DIC 2010: 1-19 - Robert Fischbach, Jens Lienig, Matthias Thiele:
Solution space investigation and comparison of modern data structures for heterogeneous 3D designs. 3DIC 2010: 1-8 - Paul D. Franzon, John M. Wilson, Ming Li:
Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications. 3DIC 2010: 1-4 - Takafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi:
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC 2010: 1-5 - Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Cache partitioning strategies for 3-D stacked vector processors. 3DIC 2010: 1-6 - Markus Gabriel, Thomas Knauer, Peter Bisson, Sumant Sood, Wilfried Bair, Jim Hermanowski:
Equipment challenges and solutions for diverse temporary bonding and de-bonding processes in 3D integration. 3DIC 2010: 1-5 - Gweltaz Gaudin, Gregory Riou, Didier Landru, Catherine Tempesta, Ionut Radu, Mariam Sadaka, Kevin Winstel, Emily Kinser, Robert Hannon:
Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment. 3DIC 2010: 1-4 - Negin Golshani, Jaber Derakhshandeh, Ryoichi Ishihara, C. I. M. Beenakker, Michael Robertson, Thomas Morrison:
Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon. 3DIC 2010: 1-4 - Matthias Gulbins, Fabian Hopsch, Peter Schneider, Bernd Straube, Wolfgang Vermeiren:
Developing digital test sequences for through-silicon vias within 3D structures. 3DIC 2010: 1-6 - Sangwook Han, David D. Wentzloff:
Wireless power transfer using resonant inductive coupling for 3D integrated ICs. 3DIC 2010: 1-5 - Harry Hedler, Thomas Scheiter, Markus Schieber, Armin Klumpp, Peter Ramm:
High performance 3D interconnects based on electrochemical etch and liquid metal fill. 3DIC 2010: 1-7 - Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma, Sayuri Kohara, Keiji Matsumoto, Hidekazu Kikuchi, Yasumitsu Orii, Toshiro Mitsuhashi, Fumiaki Yamada:
High density 3D integration by pre-applied Inter Chip Fill. 3DIC 2010: 1-5 - Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng:
Enabling power distribution network analysis flows for 3D ICs. 3DIC 2010: 1-4 - Kenzo Inagaki:
3D R&D technology for the future voyage in Japan. 3DIC 2010: 1-42 - Fumihiro Inoue, Takumi Yokoyama, Hiroshi Miyake, Shukichi Tanaka, Toshifumi Terui, Tomohiro Shimizu, Shoso Shingubara:
All-wet fabrication technology for high aspect ratio TSV using electroless barrier and seed layers. 3DIC 2010: 1-5 - Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai:
3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's. 3DIC 2010: 1-4 - Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno:
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC 2010: 1-6 - Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen:
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. 3DIC 2010: 1-4 - Moongon Jung, Sung Kyu Lim:
A study of IR-drop noise issues in 3D ICs with through-silicon-vias. 3DIC 2010: 1-7
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