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Publication search results
found 92 matches
- 1998
- Md. Altaf-Ul-Amin, Zahari Mohamed Darus:
An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs. Asian Test Symposium 1998: 318-322 - Vladimir Castro Alves, Felipe M. G. França, Edson do Prado Granja:
A BIST Scheme for Asynchronous Logic. Asian Test Symposium 1998: 27-32 - Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment. Asian Test Symposium 1998: 21-26 - Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387 - S. M. Aziz, Joarder Kamruzzaman:
Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. Asian Test Symposium 1998: 119- - Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs. Asian Test Symposium 1998: 440- - Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy:
Vector Restoration Using Accelerated Validation and Refinement. Asian Test Symposium 1998: 458-466 - Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang:
A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium 1998: 33- - Yue-Tsang Chen, Chauchin Su:
Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. Asian Test Symposium 1998: 378-382 - Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. Asian Test Symposium 1998: 244-252 - Silvia Chiusano, Fulvio Corno, Paolo Prinetto:
A Test Pattern Generation Algorithm Exploiting Behavioral Information. Asian Test Symposium 1998: 480-485 - Kin Wee Choo, Guoxiao Guo, Ben M. Chen:
Development of a Multi-Channel PC-Based Hard Disk Drive Bode-Plot Generator. Asian Test Symposium 1998: 184- - Yu-Chun Chuang, Cheng-Wen Wu:
On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. Asian Test Symposium 1998: 301-305 - Terry Corpuz:
Fast Window Test Method of Hysteresis Test. Asian Test Symposium 1998: 179-183 - Vikram Devdas, André Ivanov:
Non-Intrusive Testing of High-Speed CML Circuits. Asian Test Symposium 1998: 172-178 - Chryssa Dislis, Gerry Musgrave, Roger B. Hughes:
Formal Design Techniques - Theory and Engineering Reality. Asian Test Symposium 1998: 394-398 - Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth:
Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472- - Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium 1998: 418-423 - Mark G. Faust:
ATE Features for IDDQ Testing. Asian Test Symposium 1998: 153- - Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
Fault Detection in a Tristate System Environment. Asian Test Symposium 1998: 253-258 - Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51 - Eric Mouchel La Fosse:
A Structured Testing Approach for DSP Software. Asian Test Symposium 1998: 131- - Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell:
False-Path Removal Using Delay Fault Simulation. Asian Test Symposium 1998: 82-87 - Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439 - J. Gong, Eddie M. C. Wong:
Verification of Asynchronous Circuits with Bounded Inertial Gate Delays. Asian Test Symposium 1998: 399-401 - Ad J. van de Goor:
Answers to the Key Issues. Asian Test Symposium 1998: 520 - Zhen Guo, He Li, Shuling Guo, Dongsheng Wang:
Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer. Asian Test Symposium 1998: 413- - Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . Asian Test Symposium 1998: 467-471 - Said Hamdioui, Ad J. van de Goor:
Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. Asian Test Symposium 1998: 340-347 - Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita:
A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium 1998: 327-
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