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Alexandru Amaricai , Alin Dobre , Oana Boncalo , Andrei V. Tanase , Camelia Valuch : Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator. SACI 2011 : 433-437 export record
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journals/corr/abs-1104-0924 share record
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Alexander Yu. Vlasov : ReveR: Software Simulator of Reversible Processor with Stack. CoRR abs/1104.0924 (2011 )2010 export record
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journals/simulation/ChenS10 share record
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Yu Chen , Hessam S. Sarjoughian : A Component-based Simulator for MIPS32 Processors. Simul. 86 (5-6 ) : 271-290 (2010 )share record
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Huiwei Lv , Yuan Cheng , Lu Bai , Mingyu Chen , Dongrui Fan , Ninghui Sun : P-GAS: Parallelizing a Cycle-Accurate Event-Driven Many-Core Processor Simulator Using Parallel Discrete Event Simulation. PADS 2010 : 89-96 export record
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conf/recosoc/MollerRMIG10 share record
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Leandro Möller , André Rodrigues , Fernando Moraes , Leandro Soares Indrusiak , Manfred Glesner : Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors. ReCoSoC 2010 : 7-11 2009 share record
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Dohyung Kim , Rajesh Gupta : Cycle accurate transaction-driven simulation with multiple processor simulators. IEICE Electron. Express 6 (1 ) : 44-50 (2009 )share record
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Hui Zeng , Matt T. Yourst , Kanad Ghose , Dmitry V. Ponomarev : MPTLsim: a simulator for X86 multicore processors. DAC 2009 : 226-231 share record
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Sotiria Fytraki , Dionisios N. Pnevmatikatos : ReSim, a trace-driven, reconfigurable ILP processor simulator. DATE 2009 : 536-541 share record
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Miodrag Djukic , Nenad Cetic , Radovan Obradovic , Miroslav Popovic : An Approach to Instruction Set Compiled Simulator Development Based on a Target Processor C Compiler Back-End Design. ECBS-EERC 2009 : 32-41 2008 share record
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Kai Zheng , Yongxin Zhu , Jun Xu : Evaluation of Partitioning Methods for Stream Applications on a Heterogeneous Multi-core Processor Simulator. EUC (2) 2008 : 486-491 share record
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Kana Murale , Scot Hildebrandt , Per Bojsen , Alfonso Urzua : AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator. MTV 2008 : 81-87 2007 share record
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Cindy Norris , James T. Wilkes : YESS: a Y86 pipelined processor simulator. ACM Southeast Regional Conference 2007 : 150-155 share record
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Dohyung Kim , Soonhoi Ha , Rajesh Gupta : CATS: cycle accurate transaction-driven simulation with multiple processor simulators. DATE 2007 : 749-754 share record
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Alisson Vasconcelos de Brito , Matthias Kühnle , Elmar U. K. Melcher , Jürgen Becker : A General Purpose Partially Reconfigurable Processor Simulator (PReProS). IPDPS 2007 : 1-7 share record
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P. K. Suri , Sumit Mittal : Design of Simulator for Evaluating the Performance of a CPU-Scheduler in a Homogeneous Multiple-Processor Environment. MSV 2007 : 207-214 export record
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journals/corr/abs-0710-4643 share record
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Mehrdad Reshadi , Nikil D. Dutt : Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. CoRR abs/0710.4643 (2007 )2006 export record
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journals/tcad/ReshadiGD06 share record
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Mehrdad Reshadi , Bita Gorjiara , Nikil D. Dutt : Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12 ) : 2904-2918 (2006 )export record
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conf/europar/ColmenarGLHML06 share record
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José Manuel Colmenar , Oscar Garnica , Juan Lanchares , José Ignacio Hidalgo , Guadalupe Miñana , Sonia López : Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006 : 495-505 share record
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Fang-Ju Lin , Herming Chiueh : A Micro-architecture Simulator for Multimedia Stream Processor. ICECS 2006 : 768-771 share record
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Rajaa S. Shindi , Shaun Cooper : Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated. SIGAda 2006 : 9-14 2005 share record
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Hoonmo Yang , Moonkey Lee : Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator. J. Supercomput. 33 (1-2 ) : 19-32 (2005 )share record
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Mehrdad Reshadi , Nikil D. Dutt : Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. DATE 2005 : 786-791 2004 share record
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Yan Luo , Jun Yang , Laxmi N. Bhuyan , Li Zhao : NePSim: A Network Processor Simulator with a Power Evaluation Framework. IEEE Micro 24 (5 ) : 34-44 (2004 )export record
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conf/asiasim/NakamuraKTMS04 share record
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Shunichiro Nakamura , Toshimune Kawanishi , Sunao Tanimoto , Yohtaro Miyanishi , Seiichi Saito : Improved Processor Synchronization for Multi-processor Traffic Simulator. AsiaSim 2004 : 386-391 share record
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Martin Burtscher , Ilya Ganusov : Automatic Synthesis of High-Speed Processor Simulators. MICRO 2004 : 55-66 share record
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Anastas Misev , Marjan Gusev : Visual simulator for ILP dynamic OOO processor. WCAE 2004 : 18 2003 export record
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journals/ieiceta/TogawaKMCYO03 share record
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Nozomu Togawa , Kyosuke Kasahara , Yuichiro Miyaoka , Jinku Choi , Masao Yanagisawa , Tatsuo Ohtsuki : A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A (12 ) : 3099-3109 (2003 )share record
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Kenji Kise , Hiroki Honda , Toshitsugu Yuba : SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. Asia-Pacific Computer Systems Architecture Conference 2003 : 122-136 share record
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Darshan Thaker , Vipin Chaudhary : DSMSim: A Distributed Shared Memory Simulator for Clusters of Symmetric Multi-Processors. PDPTA 2003 : 1561-1567 share record
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Henrique Cota de Freitas , Carlos Augusto P. S. Martins : Didactic architectures and simulator for network processor learning. WCAE 2003 : 14