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8th Asia-Pacific Computer Systems Architecture Conference 2003: Aizu-Wakamatsu. Japan
- Amos Omondi, Stanislav Sedukhin:

Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings. Lecture Notes in Computer Science 2823, Springer 2003, ISBN 3-540-20122-X - Tetsuya Sato, Hitoshi Murai, Shigemune Kitawaki:

How Can the Earth Simulator Impact on Human Activities. 1-7 - Tadao Nakamura:

Toward Architecting and Designing Novel Computers. 8-13 - Doug Burger:

Designing Ultra-large Instruction Issue Windows. 14-20 - Chris R. Jesshope:

Multi-threaded Microprocessors - Evolution or Revolution. 21-45 - Victor Korneev:

The Development of System Software for Parallel Supercomputers. 46-53 - Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya:

Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. 54-68 - John Morris:

Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research. 69-85 - Amos Omondi:

Design and Implementation of Java Processors. 86-96 - Radim Ballner, Pavel Tvrdík:

MOOSS: CPU Architecture with Memory Protection and Support for OOP. 97-111 - Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga:

Reducing Access Count to Register-Files through Operand Reuse. 112-121 - Kenji Kise, Hiroki Honda, Toshitsugu Yuba:

SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. 122-136 - Qianyi Zhang, Georgios Theodoropoulos:

Towards an Asynchronous MIPS Processor. 137-150 - G. Stewart Von Itzstein, Mark Jasiunas:

On Implementing High Level Concurrency in Java. 151-165 - Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran:

Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. 166-179 - Paul Gardner-Stephen, Greg Knowles:

A Novel Architecture for Genomic Sequence Searching and Alignment. 180-192 - Sebastian Wallner:

A Reconfigurable Multi-threaded Architecture Model. 193-207 - Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, Kenichi Kuroda:

Reconfigurable Instruction-Level Parallel Processor Architecture. 208-220 - Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma

, Michèl A. J. Rosien, Paul M. Heysters:
Mapping Applications to a Coarse Grain Reconfigurable System. 221-235 - Abhinandan Sharma, Martyn A. George, David A. Kearney:

Packing with Boundary Constraints for a Reconfigurable Operating System. 236-245 - Anders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi:

Arithmetic Circuits Combining Residue and Signed-Digit Representations. 246-257 - Hooman Nikmehr, Cheng-Chew Lim:

A New On-the-fly Summation Algorithm. 258-267 - Kun-Lin Tsai

, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung:
State Reordering for Low Power Combinational Logic. 268-276 - Andreas Haeberlen

, Kevin Elphinstone:
User-Level Management of Kernel Memory. 277-289 - Cristan Szmajda, Gernot Heiser:

Variable Radix Page Table: A Page Table for Modern Architectures. 290-304 - Philip Machanick, Zunaid Patel:

L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. 305-319 - Adam Wiggins, Simon Winwood, Harvey Tuch, Gernot Heiser:

Legba: Fast Hardware Support for Fine-Grained Protection. 320-336 - Mohan G. Kabadi

, Ranjani Parthasarathi:
Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. 337-351 - Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser:

Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor. 352-364 - Sonny Tham, John Morris:

Performance of the Achilles Router. 365-379 - Philip Machanick, Brynn Andrew:

Latency Improvement in Virtual Multicasting. 380-394 - Muhammad Mahmudul Islam, Ronald Pose, Carlo Kopp:

A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks. 395-407

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