- Surya Piplani, G. S. Visweswaran, Anshul Kumar:
Impact of crosstalk and process variation on capture power reduction for at-speed test. VTS 2016: 1-6 - 2015
- Nabeeh Kandalaft, Ali Attaran, Rashid Rashidzadeh:
High speed test interface module using MEMS technology. Microelectron. Reliab. 55(2): 374-382 (2015) - Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan:
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. ACM Trans. Design Autom. Electr. Syst. 21(1): 14:1-14:25 (2015) - Xiaoqing Wen:
Power supply noise and its reduction in at-speed scan testing. ASICON 2015: 1-4 - Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin:
Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. ASP-DAC 2015: 514-519 - Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian:
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS 2015: 103-108 - Zhou Jiang, Dong Xiang, Kele Shen:
A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test. ATS 2015: 7-12 - Matthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Optimized Selection of Frequencies for Faster-Than-at-Speed Test. ATS 2015: 109-114 - Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen:
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS 2015: 79-84 - Swati Chakraborty, Duncan M. Hank Walker:
At-Speed Path Delay Test. NATW 2015: 39-42 - (Withdrawn) Diagnosis of rotor inter-turn fault of electrical machine at speed using stray flux test method. AFRICON 2015: 1-5
- 2014
- Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini:
At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs. IEEE Trans. Computers 63(3): 703-717 (2014) - Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee:
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 127-138 (2014) - Ming-Hong Tsai, Wei-Sheng Ding, Hung-Yi Hsieh, James Chien-Mo Li:
Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1980-1989 (2014) - Jose Moreira, Hubert Werkmann, Masahiro Ishida, Bernhard Roth, Volker Filsinger, Sui-Xia Yang:
An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution. ATS 2014: 218-223 - Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
At-speed interconnect testing and test-path optimization for 2.5D ICs. VTS 2014: 1-6 - Nisar Ahmed, Mohammad Tehranipoor:
Faster-than-at-Speed Test for Screening Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 73-94 - 2013
- Teresa L. McLaurin:
Creating Structural Patterns for At-Speed Testing: A Case Study. IEEE Des. Test 30(2): 66-76 (2013) - Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. 96-D(9): 2003-2011 (2013) - Yiyu Shi, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah:
Order statistics for correlated random variables and its application to at-speed testing. ACM Trans. Design Autom. Electr. Syst. 18(3): 42:1-42:20 (2013) - Jose Moreira, Bernhard Roth, Hubert Werkmann, Lars Klapproth, Michael Howieson, Mark Broman, Wend Ouedraogo, Mitchell Lin:
An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System. Asian Test Symposium 2013: 271-276 - Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - Kun-Han Tsai, Xijiang Lin:
Multicycle-aware At-speed Test Methodology. Asian Test Symposium 2013: 49 - Saman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori:
A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing. ETS 2013: 1-6 - Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP 2013: 1-6 - Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang:
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284 - Sanku Mukherjee, Srinivasaraman Chandrasekaran, Ganapathy Subramanyan E. K., Arul Sendhil:
At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems. VLSI Design 2013: 297-301 - 2012
- Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen:
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1644-1655 (2012) - Xiang Fu, Huawei Li, Xiaowei Li:
Testable Path Selection and Grouping for Faster Than At-Speed Testing. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 236-247 (2012) - Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura:
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium 2012: 1