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ORCID"Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False ..."
Koji Asada et al. (2015)
- Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian:
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS 2015: 103-108
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