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2020 – today
- 2023
[j8]Shu Wang, Yicheng Wang, Jiarong Tong, Yuqing Chang:
Fault Monitoring Based on the VLSW-MADF Test and DLPPCA for Multimodal Processes. Sensors 23(2): 987 (2023)
2010 – 2019
- 2013
- [j7]Meng Yang, Jiarong Tong, Jinmei Lai:
Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions. J. Comput. 8(10): 2520-2526 (2013) - [j6]Ying Wang, Xuegong Zhou, Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng, Jiarong Tong:
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2179-2192 (2013) - [c23]Meng Yang, Jiarong Tong, A. E. A. Almaini:
Indirect connection aware attraction for FPGA clustering (abstract only). FPGA 2013: 265 - [c22]Meng Yang, Jinmei Lai, Jiarong Tong:
Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. FPL 2013: 1-4 - 2012
- [j5]Liyun Wang, Chun Zhang, Liguang Chen, Jinmei Lai, Jiarong Tong:
A novel memristor-based rSRAM structure for multiple-bit upsets immunity. IEICE Electron. Express 9(9): 861-867 (2012) - [c21]Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong:
A partially reconfigurable architecture supporting hardware threads. FPT 2012: 269-276 - 2011
- [j4]Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang, Lingli Wang, Jiarong Tong:
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design. IEEE Trans. Circuits Syst. II Express Briefs 58-II(7): 432-436 (2011) - [c20]Kanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong:
A coarse-grained reconfigurable computing unit. ASICON 2011: 87-90 - [c19]Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He:
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA 2011: 279 - 2010
- [j3]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Accelerating Boolean Matching Using Bloom Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(10): 1775-1781 (2010) - [c18]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Building a faster boolean matcher using bloom filter. FPGA 2010: 185-188 - [c17]Kejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D. Tan, Jiarong Tong:
General switch box modeling and optimization for FPGA routing architectures. FPT 2010: 320-323 - [c16]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Engineering a scalable Boolean matching based on EDA SaaS 2.0. ICCAD 2010: 750-755
2000 – 2009
- 2009
- [c15]Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong:
A delay-optimized universal FPGA routing architecture. ASP-DAC 2009: 135-136 - 2008
- [j2]Meng Yang, Lingli Wang, Jiarong Tong, A. E. A. Almaini:
Techniques for dual forms of Reed-Muller expansion conversion. Integr. 41(1): 113-122 (2008) - [j1]Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min:
A high-performance reconfigurable VLSI architecture for vbsme in H.264. IEEE Trans. Consumer Electron. 54(3): 1338-1345 (2008) - [c14]Yabin Wang, Jing Xie, Jinmei Lai, Jiarong Tong:
Design and implementation of the configuration circuit for FDP FPGA. APCCAS 2008: 696-700 - [c13]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A novel dynamic reconfigurable VLSI architecture for H.264 transforms. APCCAS 2008: 1810-1813 - [c12]Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni:
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. DAC 2008: 223-226 - [c11]Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong:
Variational capacitance modeling using orthogonal polynomial method. ACM Great Lakes Symposium on VLSI 2008: 23-28 - [c10]Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong:
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. ICECS 2008: 486-489 - [c9]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A high-performance reconfigurable 2-D transform architecture for H.264. ICECS 2008: 606-609 - 2007
- [c8]Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng:
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. ASP-DAC 2007: 209-214 - 2005
- [c7]Yirong OuYang, Jiarong Tong:
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only). FPGA 2005: 263 - [c6]Wen Yujie, Jiarong Tong, Charles C. Chiang:
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only). FPGA 2005: 269 - 2004
- [c5]Jian Wang, Xuan Zeng, Wei Cai, Charles C. Chiang, Jiarong Tong, Dian Zhou:
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. ISCAS (5) 2004: 321-324 - [c4]Lihong Feng, Xuan Zeng, Jiarong Tong, Charles C. Chiang, Dian Zhou:
Two-sided projection method in variational equation model order reduction of nonlinear circuits. ISCAS (4) 2004: 816-819 - 2003
- [c3]Binlin Guo, Jiarong Tong:
A SC-based novel configurable analog cell. FPGA 2003: 243
1990 – 1999
- 1999
- [c2]Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang:
An Analytical Delay Model for SRAM-Based FPGA Interconnections. ASP-DAC 1999: 101-104 - 1998
- [c1]Rongzheng Zhou, Jiarong Tong, Pushan Tang:
FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm. ASP-DAC 1998: 513-518
Coauthor Index
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