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2020 – today
- 2024
[j51]Yu-Han Sun, Chiang Lo-Hsuan Lee, Tian-Sheuan Chang
:
IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering for Versatile Video Coding. IEEE Open J. Circuits Syst. 5: 17-27 (2024)- [j50]Ci-Hao Wu, Tian-Sheuan Chang:
A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices. IEEE Open J. Circuits Syst. 5: 128-140 (2024) - [j49]Tun-Hao Yang, Tian-Sheuan Chang:
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator With Decoupled Asymmetric Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 670-679 (2024) - [j48]Yuan Yao, Tian-Sheuan Chang:
ASC: Adaptive Scale Feature Map Compression for Deep Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1417-1428 (2024) - [j47]Chih-Chia Hsu, Tian-Sheuan Chang:
ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1693-1705 (2024) - [j46]Chih-Chyau Yang, Tian-Sheuan Chang:
A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3203-3213 (2024) - [c83]Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang:
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. DATE 2024: 1-6 - [c82]Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang:
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. ISCAS 2024: 1-5 - [c81]I-Hsuan Li, Tian-Sheuan Chang:
Dynamic Gradient Sparse Update for Edge Training. ISCAS 2024: 1-5 - [c80]Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou:
Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j45]Chih-Chyau Yang, Tian-Sheuan Chang:
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation. IEEE Trans. Very Large Scale Integr. Syst. 31(3): 310-319 (2023) - [j44]An-Jung Huang, Jo-Hsuan Hung, Tian-Sheuan Chang:
Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 802-811 (2023) - [c79]Yan-Cheng Guo, Wei-Tien Lin, Tuo-Hung Hou, Tian-Sheuan Chang:
FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices. ISCAS 2023: 1-5 - [i26]Tun-Hao Yang, Tian-Sheuan Chang:
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator with Decoupled Asymmetric Convolution. CoRR abs/2308.15807 (2023) - [i25]Yuan Yao, Tian-Sheuan Chang:
ASC: Adaptive Scale Feature Map Compression for Deep Neural Network. CoRR abs/2312.08176 (2023) - [i24]Chih-Chyau Yang, Tian-Sheuan Chang:
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation. CoRR abs/2312.09580 (2023) - [i23]Yu-Han Sun, Chiang Lo-Hsuan Lee, Tian-Sheuan Chang:
IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering For Versatile Video Coding. CoRR abs/2312.09799 (2023) - [i22]Chia Shuo Chang, Tian Sheuan Chang, Jiun-Lin Yan, Li Ko:
All Attention U-NET for Semantic Segmentation of Intracranial Hemorrhages In Head CT Images. CoRR abs/2312.10483 (2023) - 2022
- [j43]Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
Hardware-Robust In-RRAM-Computing for Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 547-556 (2022) - [j42]Hong-Han Lien, Tian-Sheuan Chang:
Sparse Compressed Spiking Neural Network Accelerator for Object Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 2060-2069 (2022) - [j41]Tzu-Hsuan Chen, Tian Sheuan Chang:
RangeSeg: Range-Aware Real Time Segmentation of 3D LiDAR Point Clouds. IEEE Trans. Intell. Veh. 7(1): 93-101 (2022) - [j40]Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang, Shang-Hong Tsai, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang:
A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic. IEEE Trans. Very Large Scale Integr. Syst. 30(6): 816-825 (2022) - [j39]Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou:
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1184-1192 (2022) - [c78]Hong-Yi Wang, Tian-Sheuan Chang:
Row-wise Accelerator for Vision Transformer. AICAS 2022: 399-402 - [c77]Chia Shuo Chang, Tian Sheuan Chang, Jiun-Lin Yan, Li Ko:
All Attention U-NET for Semantic Segmentation of Intracranial Hemorrhages In Head CT Images. BioCAS 2022: 600-604 - [c76]An-Jung Huang, Kai-Chieh Hsu, Tian-Sheuan Chang:
A Real Time Super Resolution Accelerator with Tilted Layer Fusion. ISCAS 2022: 2665-2669 - [c75]Dun-Hao Yang, Tian-Sheuan Chang:
BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention. ISCAS 2022: 2821-2825 - [c74]Shu-Hung Kuo, Tian-Sheuan Chang:
PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting. ISCAS 2022: 2968-2972 - [c73]Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT 2022: 1-4 - [i21]Dun-Hao Yang, Tian-Sheuan Chang:
BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention. CoRR abs/2205.00777 (2022) - [i20]Hong-Han Lien, Tian-Sheuan Chang:
Sparse Compressed Spiking Neural Network Accelerator for Object Detection. CoRR abs/2205.00778 (2022) - [i19]Hsu-Tung Shih, Tian-Sheuan Chang:
Zebra: Memory Bandwidth Reduction for CNN Accelerators With Zero Block Regularization of Activation Maps. CoRR abs/2205.00779 (2022) - [i18]Hong-Han Lien, Chung-Wei Hsu, Tian-Sheuan Chang:
VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator. CoRR abs/2205.00780 (2022) - [i17]Shu-Hung Kuo, Tian-Sheuan Chang:
PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting. CoRR abs/2205.01569 (2022) - [i16]Tzu-Hsuan Chen, Tian Sheuan Chang:
RangeSeg: Range-Aware Real Time Segmentation of 3D LiDAR Point Clouds. CoRR abs/2205.01570 (2022) - [i15]Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang, Shang-Hong Tsai, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang:
A Real Time 1280x720 Object Detection Chip With 585MB/s Memory Traffic. CoRR abs/2205.01571 (2022) - [i14]Hsiao-Shan Huang, Tian-Sheuan Chang, Jhih-Yi Wu:
A Secure File Sharing System Based on IPFS and Blockchain. CoRR abs/2205.01728 (2022) - [i13]Chih-Chyau Yang, Tian-Sheuan Chang:
Pre-RTL DNN Hardware Evaluator With Fused Layer Support. CoRR abs/2205.01729 (2022) - [i12]Kuo-Wei Chang, Tian-Sheuan Chang:
Efficient Accelerator for Dilated and Transposed Convolution with Decomposition. CoRR abs/2205.02103 (2022) - [i11]Kuo-Wei Chang, Tian-Sheuan Chang:
VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network. CoRR abs/2205.02270 (2022) - [i10]Kuo-Wei Chang, Tian-Sheuan Chang:
VSCNN: Convolution Neural Network Accelerator With Vector Sparsity. CoRR abs/2205.02271 (2022) - [i9]Jien-De Sui, Tian-Sheuan Chang:
IMU Based Deep Stride Length Estimation With Self-Supervised Learning. CoRR abs/2205.02977 (2022) - [i8]Yian Chen, Jien-De Sui, Tian-Sheuan Chang:
Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model. CoRR abs/2205.03234 (2022) - [i7]Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
Hardware-Robust In-RRAM-Computing for Object Detection. CoRR abs/2205.03996 (2022) - [i6]An-Jung Huang, Kai-Chieh Hsu, Tian-Sheuan Chang:
A Real Time Super Resolution Accelerator with Tilted Layer Fusion. CoRR abs/2205.03997 (2022) - [i5]Hong-Yi Wang, Tian-Sheuan Chang:
Row-wise Accelerator for Vision Transformer. CoRR abs/2205.03998 (2022) - [i4]Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou:
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization. CoRR abs/2205.04665 (2022) - [i3]Jien-De Sui, Tian Sheuan Chang:
Deep Gait Tracking With Inertial Measurement Unit. CoRR abs/2205.04666 (2022) - [i2]Jien-De Sui, Wei-Han Chen, Tzyy-Yuang Shiang, Tian-Sheuan Chang:
Real-Time Wearable Gait Phase Segmentation For Running And Walking. CoRR abs/2205.04668 (2022) - 2021
- [c72]Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou:
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC 2021: 1-3 - [c71]Hong-Han Lien, Chung-Wei Hsu, Tian-Sheuan Chang:
VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator. ISCAS 2021: 1-5 - [c70]Chih-Chyau Yang, Tian-Sheuan Chang:
Pre-RTL DNN Hardware Evaluator With Fused Layer Support. ISOCC 2021: 83-84 - 2020
- [j38]Yi-Chun Chen, Tian-Sheuan Chang:
Image Synthesis With Efficient Defocus Blur for Stereoscopic Displays. IEEE Access 8: 176304-176312 (2020) - [j37]Kuo-Wei Chang, Tian-Sheuan Chang:
VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 145-154 (2020) - [c69]Yian Chen, Jien-De Sui, Tian-Sheuan Chang:
Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model. ICCE-TW 2020: 1-2 - [c68]Hsiao-Shan Huang, Tian-Sheuan Chang, Jhih-Yi Wu:
A Secure File Sharing System Based on IPFS and Blockchain. IECC 2020: 96-100 - [c67]Kuo-Wei Chang, Tian-Sheuan Chang:
Efficient Accelerator for Dilated and Transposed Convolution with Decomposition. ISCAS 2020: 1-5 - [c66]Hsu-Tung Shih, Tian-Sheuan Chang:
Zebra: Memory Bandwidth Reduction for CNN Accelerators with Zero Block Regularization of Activation Maps. ISCAS 2020: 1-5 - [c65]Jien-De Sui, Wei-Han Chen, Tzyy-Yuang Shiang, Tian-Sheuan Chang:
Real-Time Wearable Gait Phase Segmentation for Running And Walking. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c64]Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou:
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. DAC 2019: 30 - [c63]Kuo-Wei Chang, Tian-Sheuan Chang:
VSCNN: Convolution Neural Network Accelerator with Vector Sparsity. ISCAS 2019: 1-5 - [c62]Hong Ming Chiu, Kuan-Chih Lin, Tian Sheuan Chang:
Run Time Adaptive Network Slimming for Mobile Environments. ISCAS 2019: 1-4 - 2018
- [j36]Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou:
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 116-124 (2018) - [j35]Yue-Jin Lin, Tian Sheuan Chang:
Data and Hardware Efficient Design for Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1642-1651 (2018) - [c61]Kevin C. Tseng, Alice M. K. Wong, Chung-Yu Wu, Tian-Sheuan Chang, Yu-Cheng Pei, Jean-Lon Chen:
A Scoping Study on the Development of an Interactive Upper-Limb Rehabilitation System Framework for Patients with Stroke. HCI (8) 2018: 386-393 - [c60]Tian-Sheuan Chang:
End-to-end hardware accelerator for deep convolutional neural network. VLSI-DAT 2018: 1 - 2017
- [c59]Hung-Cheng Chen, Tian-Sheuan Chang:
Fast rate distortion optimization with adaptive context group modeling for HEVC. ISCAS 2017: 1-4 - [i1]Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou:
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse. CoRR abs/1712.05895 (2017) - 2016
- [j34]Pai-Tse Chiang, Yi-Ching Ting, Hsuan-ku Chen, Shiau-Yu Jou, I-Wen Chen, Hang-Chiu Fang, Tian-Sheuan Chang:
A QFHD 30-frames/s HEVC Decoder Design. IEEE Trans. Circuits Syst. Video Technol. 26(4): 724-735 (2016) - [c58]Yi-Chun Chen, Tian-Sheuan Chang:
Perceptual oriented depth cue enhancement for stereoscopic view synthesis. 3DTV-Conference 2016: 1-4 - [c57]Han-Chiou Fang, Hung-Cheng Chen, Tian-Sheuan Chang:
Fast intra prediction algorithm and design for high efficiency video coding. ISCAS 2016: 1770-1773 - 2015
- [j33]Shiaw-Yu Jou, Shan-Jung Chang, Tian-Sheuan Chang:
Fast Motion Estimation Algorithm and Design for Real Time QFHD High Efficiency Video Coding. IEEE Trans. Circuits Syst. Video Technol. 25(9): 1533-1544 (2015) - [c56]Jia-Hao Chang, Tian Sheuan Chang:
Fast rate distortion optimization design for HEVC intra coding. DSP 2015: 473-476 - [c55]Tsung-Pen Chou, Wan-Ru Wang, Tian Sheuan Chang:
Low complexity real time BCI for stroke rehabilitation. DSP 2015: 809-812 - [c54]Chih-Chung Fang, I-Wen Chen, Tian-Sheuan Chang:
A hardware-efficient deblocking filter design for HEVC. ISCAS 2015: 1786-1789 - 2014
- [j32]Cheng-Wen Wei, Cheng-Chun Tsai, FanJiang Yi, Tian-Sheuan Chang, Shyh-Jye Jou:
Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application. IET Circuits Devices Syst. 8(6): 516-525 (2014) - [j31]Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang:
Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing. IEEE ACM Trans. Audio Speech Lang. Process. 22(8): 1248-1259 (2014) - [j30]Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang:
Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing". IEEE ACM Trans. Audio Speech Lang. Process. 22(12): 2256 (2014) - [c53]Shuo-Wen Hsu, Tian Sheuan Chang:
A real time 1080P 30FPS Gaussian Mixture Modeling design for background subtraction and object extraction. ICCE-TW 2014: 185-186 - [c52]Yi-Ching Ting, Tian-Sheuan Chang:
Gradient-based PU size selection for HEVC intra prediction. ISCAS 2014: 1929-1932 - [c51]Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang:
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC 2014: 76-81 - 2013
- [j29]Gwo-Long Li, Tian-Sheuan Chang:
An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension. IEEE Trans. Circuits Syst. Video Technol. 23(11): 1837-1848 (2013) - [j28]Liang-Chi Chiu, Tian-Sheuan Chang, Jiun-Yen Chen, Nelson Yen-Chung Chang:
Fast SIFT Design for Real-Time Visual Feature Extraction. IEEE Trans. Image Process. 22(8): 3158-3167 (2013) - [j27]Jui-Hung Hsieh, Tian-Sheuan Chang:
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 33-42 (2013) - [j26]Gwo-Long Li, Tzu-Yu Chen, Meng-Wei Shen, Meng-Hsun Wen, Tian-Sheuan Chang:
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 636-647 (2013) - [c50]Pai-Tse Chiang, Tian-Sheuan Chang:
A reconfigurable inverse transform architecture design for HEVC decoder. ISCAS 2013: 1006-1009 - [c49]Pai-Tse Chiang, Tian-Sheuan Chang:
Fast zero block detection and early CU termination for HEVC Video Coding. ISCAS 2013: 1640-1643 - [c48]Shiau-Yu Jou, Tian-Sheuan Chang:
Fast prediction unit selection for HEVC fractional pel motion estimation design. SiPS 2013: 247-250 - [p1]Yu-Cheng Tseng, Tian-Sheuan Chang:
Real-Time Disparity Estimation Engine for High-Definition 3 DTV Applications. Emerging Technologies for 3D Video 2013: 468-485 - 2012
- [j25]Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang:
A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder. IEEE Trans. Circuits Syst. Video Technol. 22(2): 272-281 (2012) - [j24]Gwo-Long Li, Yu-Chen Chen, Yuan-Hsin Liao, Po-Yuan Hsu, Meng-Hsun Wen, Tian-Sheuan Chang:
A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder. IEEE Trans. Circuits Syst. Video Technol. 22(4): 626-635 (2012) - [j23]Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang:
A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video. IEEE Trans. Circuits Syst. Video Technol. 22(11): 1604-1610 (2012) - [j22]Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou:
Sub µW Noise Reduction for CIC Hearing Aids. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 937-947 (2012) - [c47]Yi-Ching Ting, Tian-Sheuan Chang:
Fast intra prediction algorithm with transform domain edge detection for HEVC. APCCAS 2012: 144-147 - [c46]Jou-Ling Chen, Jhih-Cing Sun, Yi-Hung Shen, Tzu-Hsien Sang, Tian-Sheuan Chang, Shyh-Jye Jou:
A low-power body-channel communication system for binaural hearing aids. BioCAS 2012: 100-103 - [c45]Hsuan-ku Chen, Tian-Sheuan Chang:
A high throughput CAVLC design for HEVC. ISCAS 2012: 1919-1922 - [c44]Shuo-Wen Hsu, Tian-Sheuan Chang:
A low complexity speech coder for binaural communication in hearing aids. ISCAS 2012: 2801-2804 - [c43]Yu-Cheng Tseng, Tian-Sheuan Chang:
Fast disparity estimation for 3DTV applications. VCIP 2012: 1-5 - [c42]Liang-Chi Chiu, Tian-Sheuan Chang:
A lossless embedded compression codec engine for HD video decoding. VLSI-DAT 2012: 1-4 - 2011
- [j21]Jui-Hung Hsieh, Wei-Cheng Tai, Tian-Sheuan Chang:
Memory bandwidth-scalable motion estimation for mobile video coding. EURASIP J. Adv. Signal Process. 2011: 126 (2011) - [j20]Ying-Rung Horng, Yu-Cheng Tseng, Tian-Sheuan Chang:
VLSI Architecture for Real-Time HD1080p View Synthesis Engine. IEEE Trans. Circuits Syst. Video Technol. 21(9): 1329-1340 (2011) - [j19]Yu-Cheng Tseng, Po-Hsiung Hsu, Tian-Sheuan Chang:
A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering. IEEE Trans. Image Process. 20(11): 3231-3241 (2011) - [c41]Lu Zhang, Ke Zhang, Tian Sheuan Chang, Gauthier Lafruit, Georgi Krasimirov Kuzmanov, Diederik Verkest:
Real-time high-definition stereo matching on FPGA. FPGA 2011: 55-64 - [c40]Jui-Hung Hsieh, Tian-Sheuan Chang:
Bandwidth-constrained motion estimation for real-time mobile video application. DSP 2011: 1-6 - [c39]Gwo-Long Li, Tian-Sheuan Chang:
An efficient mode pre-selection algorithm for H.264/AVC scalable video extension fractional motion estimation. DSP 2011: 1-5 - [c38]Yu-Cheng Tseng, Tian-Sheuan Chang:
Fast algorithm for local stereo matching in disparity estimation. DSP 2011: 1-6 - [c37]Fu-Jen Chang, Yu-Cheng Tseng, Tian-Sheuan Chang:
A 94fps view synthesis engine for HD1080p video. VCIP 2011: 1-4 - 2010
- [j18]Nelson Yen-Chung Chang, Tsung-Hsien Tsai, Po-Hsiung Hsu, Yi-Chun Chen, Tian-Sheuan Chang:
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight. IEEE Trans. Circuits Syst. Video Technol. 20(6): 792-805 (2010) - [j17]Yu-Cheng Tseng, Tian-Sheuan Chang:
Architecture Design of Belief Propagation for Real-Time Disparity Estimation. IEEE Trans. Circuits Syst. Video Technol. 20(11): 1555-1564 (2010) - [j16]Gwo-Long Li, Tian-Sheuan Chang:
RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access. IEEE Trans. Circuits Syst. Video Technol. 20(11): 1565-1576 (2010) - [c36]Cheng-Wen Wei, Cheng-Chun Tsai, Tian-Sheuan Chang, Shyh-Jye Jou:
Perceptual multiband spectral subtraction for noise reduction in hearing aids. APCCAS 2010: 692-695 - [c35]Yu-Chen Chen, Gwo-Long Li, Tian-Sheuan Chang:
Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. ISCAS 2010: 665-668 - [c34]Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang:
A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoder. ISCAS 2010: 2007-2010 - [c33]Ying-Rung Horng, Yu-Cheng Tseng, Tian-Sheuan Chang:
Stereoscopic images generation with directional Gaussian filter. ISCAS 2010: 2650-2653 - [c32]Po-Hsiung Hsu, Yu-Cheng Tseng, Tian-Sheuan Chang:
Low memory cost bilateral filtering using stripe-based sliding integral histogram. ISCAS 2010: 3120-3123 - [c31]Yu-Cheng Tseng, Po-Hsiung Hsu, Tian-Sheuan Chang:
Fast stereo matching with predictive search range. PCS 2010: 506-509
2000 – 2009
- 2009
- [j15]Nelson Yen-Chung Chang, Ying-Ze Liao, Tian-Sheuan Chang:
Analysis of shared-link AXI. IET Comput. Digit. Tech. 3(4): 373-383 (2009) - [j14]Yu-Kun Lin, Chun-Wei Ku, De-Wei Li, Tian-Sheuan Chang:
A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder. IEEE Trans. Circuits Syst. Video Technol. 19(3): 432-436 (2009) - [c30]Wei-Cheng Tai, Gwo-Long Li, Tian-Sheuan Chang:
Bandwidth-rate-distortion optimized motion estimation. ICME 2009: 161-164 - [c29]Yu-Cheng Tseng, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Low-memory Cost Belief Propagation Architecture for Disparity Estimation. ISCAS 2009: 153-156 - [c28]Tzu-Yu Chen, Gwo-Long Li, Tian-Sheuan Chang:
Memory Analysis for H.264/AVC Scalable Extension Encoder. ISCAS 2009: 361-364 - [c27]Meng-Wei Shen, Gwo-Long Li, Tian-Sheuan Chang:
A Memory Efficient Fine Grain Scalability Coefficient Encoding Method for H.264/AVC Scalable Video Extension. ISCAS 2009: 3034-3037 - 2008
- [j13]Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, Tian-Sheuan Chang:
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1526-1535 (2008) - [j12]Hui-Cheng Hsu, Kun-Bin Lee, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding. IEEE Trans. Circuits Syst. Video Technol. 18(3): 375-386 (2008) - [j11]Sin-Bor Wang, Tian-Sheuan Chang:
Adaptive De-Interlacing With Robust Overlapped Block Motion Compensation. IEEE Trans. Circuits Syst. Video Technol. 18(10): 1437-1440 (2008) - [c26]Yu-Cheng Tseng, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Block-based belief propagation with in-place message updating for stereo vision. APCCAS 2008: 918-921 - [c25]Nelson Yen-Chung Chang, Yu-Cheng Tseng, Tian-Sheuan Chang:
Analysis of color space and similarity measure impact on stereo block matching. APCCAS 2008: 926-929 - [c24]Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang:
A 242mW, 10mm21080p H.264/AVC high profile encoder chip. DAC 2008: 78-83 - [c23]Tsung-Hsien Tsai, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Data reuse analysis of local stereo matching. ISCAS 2008: 812-815 - [c22]Jing-Chu Chan, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision. ISCAS 2008: 3478-3481 - [c21]Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang:
A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip. ISSCC 2008: 314-315 - 2007
- [j10]Yu-Jen Wang, Chao-Chung Cheng, Tian-Sheuan Chang:
A Fast Algorithm and Its VLSI Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding. IEEE Trans. Circuits Syst. Video Technol. 17(5): 578-583 (2007) - [c20]Jian-Long Chen, Yu-Kun Lin, Tian-Sheuan Chang:
A Low Cost Context Adaptive Arithmetic Coder for H.264/MPEG-4 AVC Video Coding. ICASSP (2) 2007: 105-108 - [c19]Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang:
PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding. ICASSP (2) 2007: 385-388 - [c18]De-Wei Li, Chun-Wei Ku, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang:
A 61MHz 72K Gates 1280x720 30FPS H.264 Intra Encoder. ICASSP (2) 2007: 801-804 - [c17]Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang:
SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding. ICASSP (1) 2007: 1185-1188 - [c16]Yu-Cheng Tseng, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Low Memory Cost Block-Based Belief Propagation for Stereo Correspondence. ICME 2007: 1415-1418 - [c15]Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang:
Real-Time DSP Implementation on Local Stereo Matching. ICME 2007: 2090-2093 - [c14]Guo-Shiuan Yu, Tian-Sheuan Chang:
Optimal Data Mapping for Motion Compensation in H.264 Video Decoding. SiPS 2007: 505-508 - 2006
- [j9]Chao-Chung Cheng, Tian-Sheuan Chang, Kun-Bin Lee:
An in-place architecture for the deblocking filter in H.264/AVC. IEEE Trans. Circuits Syst. II Express Briefs 53-II(7): 530-534 (2006) - [j8]Esam A. Al Qaralleh, Tian-Sheuan Chang, Kun-Bin Lee:
An Efficient Binary Motion Estimation Algorithm and its Architecture for MPEG-4 Shape Encoding. IEEE Trans. Circuits Syst. Video Technol. 16(7): 859-868 (2006) - [j7]C.-W. Ku, C.-C. Cheng, G.-S. Yu, M.-C. Tsai, Tian-Sheuan Chang:
A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications. IEEE Trans. Circuits Syst. Video Technol. 16(8): 917-928 (2006) - [j6]Esam A. Al Qaralleh, Tian-Sheuan Chang:
Fast Variable Block Size Motion Estimation by Adaptive Early Termination. IEEE Trans. Circuits Syst. Video Technol. 16(8): 1021-1026 (2006) - [j5]Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Combined Frame Memory Motion Compensation for Video Coding. IEEE Trans. Circuits Syst. Video Technol. 16(10): 1280-1285 (2006) - [c13]Min-Chi Tsai, Tian-Sheuan Chang:
High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding. APCCAS 2006: 586-589 - [c12]Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang:
A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding. APCCAS 2006: 1244-1247 - [c11]Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang:
A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding. APCCAS 2006: 1248-1251 - [c10]Jia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang:
A Display Order Oriented Scalable Video Decoder. APCCAS 2006: 1976-1979 - [c9]Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang:
Algorithms and DSP implementation of H.264/AVC. ASP-DAC 2006: 742-749 - [c8]Chao-Chung Cheng, Chun-Wei Ku, Tian-Sheuan Chang:
A 1280×720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder. ISCAS 2006 - [c7]Yu-Jen Wang, Chao-Chung Cheng, Tian-Sheuan Chang:
A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC. ISCAS 2006 - [c6]Guo-Shiuan Yu, Tian-Sheuan Chang:
A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264. ISCAS 2006 - 2005
- [j4]Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen:
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. IEICE Trans. Electron. 88-C(5): 1061-1069 (2005) - [j3]Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen:
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. IEEE Trans. Circuits Syst. Video Technol. 15(3): 445-453 (2005) - [c5]Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang:
A bandwidth efficient subsampling-based block matching architecture for motion estimation. ASP-DAC 2005: 7-8 - [c4]Yu-Kun Lin, Tian-Sheuan Chang:
Fast block type decision algorithm for intra prediction in H.264 FRext. ICIP (1) 2005: 585-588 - [c3]Chao-Chung Cheng, Tian-Sheuan Chang:
Fast three step intra prediction algorithm for 4×4 blocks in H.264. ISCAS (2) 2005: 1509-1512 - [c2]Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Combined frame memory architecture for motion compensation in video decoding. ISCAS (2) 2005: 1806-1809 - 2002
- [j2]Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen:
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. 12(1): 61-72 (2002) - 2000
- [j1]Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen:
A simple processor core design for DCT/IDCT. IEEE Trans. Circuits Syst. Video Technol. 10(3): 439-447 (2000)
1990 – 1999
- 1998
- [c1]Tian-Sheuan Chang, Chein-Wei Jen:
Low power FIR filter realization with differential coefficients and input. ICASSP 1998: 3009-3012
Coauthor Index
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