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ORCIDAndré Seznec
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- affiliation: IRISA/INRIA, Rennes, France
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2020 – today
- 2024
[c86]Bhargav Reddy Godala
, Sankara Prasad Ramesh, Gilles A. Pokam, Jared Stark, André Seznec, Dean M. Tullsen, David I. August:
PDIP: Priority Directed Instruction Prefetching. ASPLOS (2) 2024: 846-861- 2021
- [j44]Kleovoulos Kalaitzidis, André Seznec:
Leveraging Value Equality Prediction for Value Speculation. ACM Trans. Archit. Code Optim. 18(1): 13:1-13:20 (2021) - [j43]Daniel Rodrigues Carvalho, André Seznec:
Understanding Cache Compression. ACM Trans. Archit. Code Optim. 18(3): 36:1-36:27 (2021) - [c85]Daniel Rodrigues Carvalho, André Seznec:
Conciliating Speed and Efficiency on Cache Compressors. ICCD 2021: 442-446 - [c84]Daniel Rodrigues Carvalho, André Seznec:
A Case for Partial Co-allocation Constraints in Compressed Caches. SAMOS 2021: 65-77 - 2020
- [j42]Anita Tino, Caroline Collange, André Seznec:
SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores. ACM Trans. Archit. Code Optim. 17(2): 15:1-15:23 (2020)
2010 – 2019
- 2019
- [c83]Kleovoulos Kalaitzidis, André Seznec:
Value Speculation through Equality Prediction. ICCD 2019: 694-697 - [c82]Niloofar Charmchi, Caroline Collange, André Seznec:
Compressed Cache Layout Aware Prefetching. SBAC-PAD 2019: 25-28 - 2018
- [j41]Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec:
DITVA: Dynamic Inter-Thread Vectorization Architecture. J. Parallel Distributed Comput. 120: 267-281 (2018) - [c81]Biswabandan Panda, André Seznec:
Synergistic cache layout for reuse and compression. PACT 2018: 4:1-4:13 - [c80]Arthur Perais, André Seznec:
Cost effective speculation with the omnipredictor. PACT 2018: 25:1-25:13 - 2017
- [j40]Arthur Perais, André Seznec:
Storage-Free Memory Dependency Prediction. IEEE Comput. Archit. Lett. 16(2): 149-152 (2017) - [j39]Aswinkumar Sridharan, André Seznec:
Dynamic and discrete cache insertion policies for managing shared last level caches in large multicores. J. Parallel Distributed Comput. 106: 215-226 (2017) - [j38]Fernando A. Endo, Arthur Perais, André Seznec:
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE. ACM Trans. Archit. Code Optim. 14(2): 18:1-18:24 (2017) - [j37]Aswinkumar Sridharan, Biswabandan Panda, André Seznec:
Band-Pass Prefetching: An Effective Prefetch Management Mechanism Using Prefetch-Fraction Metric in Multi-Core Systems. ACM Trans. Archit. Code Optim. 14(2): 19:1-19:27 (2017) - [c79]Arjun Suresh, Erven Rohou, André Seznec:
Compile-time function memoization. CC 2017: 45-54 - 2016
- [j36]André Seznec, Joshua San Miguel, Jorge Albericio:
Practical Multidimensional Branch Prediction. IEEE Micro 36(3): 10-19 (2016) - [j35]Somayeh Sardashti, André Seznec, David A. Wood:
Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache. ACM Trans. Archit. Code Optim. 13(3): 27:1-27:25 (2016) - [j34]Arthur Perais, André Seznec:
EOLE: Combining Static and Dynamic Scheduling Through Value Prediction to Reduce Complexity and Increase Performance. ACM Trans. Comput. Syst. 34(2): 4:1-4:33 (2016) - [c78]Arthur Perais, André Seznec:
Cost effective physical register sharing. HPCA 2016: 694-706 - [c77]Aswinkumar Sridharan, André Seznec:
Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores. IPDPS 2016: 822-831 - [c76]Biswabandan Panda, André Seznec:
Dictionary sharing: An efficient cache compression scheme for compressed caches. MICRO 2016: 1:1-1:12 - [c75]Arthur Perais, Fernando A. Endo, André Seznec:
Register sharing for equality prediction. MICRO 2016: 4:1-4:12 - [c74]Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec:
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP. SBAC-PAD 2016: 18-25 - 2015
- [j33]Ricardo A. Velásquez, Pierre Michaud, André Seznec:
BADCO: Behavioral Application-Dependent Superscalar Core Models. Int. J. Parallel Program. 43(1): 130-157 (2015) - [j32]Arthur Perais, André Seznec:
EOLE: Toward a Practical Implementation of Value Prediction. IEEE Micro 35(3): 114-124 (2015) - [j31]Arjun Suresh, Bharath Narasimha Swamy, Erven Rohou, André Seznec:
Intercepting Functions for Memoization: A Case Study Using Transcendental Functions. ACM Trans. Archit. Code Optim. 12(2): 18:18:1-18:18:23 (2015) - [j30]Pierre Michaud, Andrea Mondelli, André Seznec:
Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters. ACM Trans. Archit. Code Optim. 12(3): 28:1-28:22 (2015) - [c73]Surya Narayanan, Bharath Narasimha Swamy, André Seznec:
An empirical high level performance model for future many-cores. Conf. Computing Frontiers 2015: 1:1-1:8 - [c72]Erven Rohou, Bharath Narasimha Swamy, André Seznec:
Branch prediction and the performance of interpreters: don't trust folklore. CGO 2015: 103-114 - [c71]Surya Narayanan, André Seznec:
Sequential and Parallel Code Sections are Different: they may require different Processors. PARMA-DITAM@HiPEAC 2015: 13-18 - [c70]Arthur Perais, André Seznec:
BeBoP: A cost effective predictor infrastructure for superscalar value prediction. HPCA 2015: 13-25 - [c69]Misel-Myrto Papadopoulou, Xin Tong, André Seznec, Andreas Moshovos:
Prediction-based superpage-friendly TLB designs. HPCA 2015: 210-222 - [c68]Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten:
Cost-effective speculative scheduling in high performance processors. ISCA 2015: 247-259 - [c67]Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, André Seznec, Pierre Michaud:
Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO 2015: 334-346 - [c66]André Seznec, Joshua San Miguel, Jorge Albericio:
The inner most loop iteration counter: a new dimension in branch history. MICRO 2015: 347-357 - 2014
- [j29]Nathanaël Prémillieu, André Seznec:
Efficient Out-of-Order Execution of Guarded ISAs. ACM Trans. Archit. Code Optim. 11(4): 41:1-41:21 (2014) - [c65]Arthur Perais, André Seznec:
Practical data value speculation for future high-end processors. HPCA 2014: 428-439 - [c64]Arthur Perais, André Seznec:
EOLE: Paving the way for an effective implementation of value prediction. ISCA 2014: 481-492 - [c63]Somayeh Sardashti, André Seznec, David A. Wood:
Skewed Compressed Caches. MICRO 2014: 331-342 - [c62]Surya Narayanan, Bharath Narasimha Swamy, André Seznec:
Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era. SBAC-PAD (Workshops) 2014: 36-41 - [c61]Bharath Narasimha Swamy, Alain Ketterlin, André Seznec:
Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores. SBAC-PAD 2014: 214-221 - 2013
- [c60]André Seznec, François Bodin:
Message from the program chairs. PACT 2013 - [c59]Junjie Lai, André Seznec:
Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs. CGO 2013: 4:1-4:10 - [c58]Ricardo A. Velásquez, Pierre Michaud, André Seznec:
Selecting benchmark combinations for the evaluation of multicore throughput. ISPASS 2013: 173-182 - [c57]André Seznec:
Faster unicores are still needed. ICSAMOS 2013 - [e4]Christian Fensch, Michael F. P. O'Boyle, André Seznec, François Bodin:
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, United Kingdom, September 7-11, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-1018-2 [contents] - 2012
- [j28]Nathanaël Prémillieu, André Seznec:
SYRANT: SYmmetric resource allocation on not-taken and taken paths. ACM Trans. Archit. Code Optim. 8(4): 43:1-43:20 (2012) - [c56]Junjie Lai, André Seznec:
Break down GPU execution time with an analytical method. RAPIDO 2012: 33-39 - [c55]Benjamin Lesage, Isabelle Puaut, André Seznec:
PRETI: partitioned real-time shared cache for mixed-criticality real-time systems. RTNS 2012: 171-180 - [c54]Ricardo A. Velásquez, Pierre Michaud, André Seznec:
BADCO: Behavioral Application-Dependent Superscalar Core model. ICSAMOS 2012: 58-67 - 2011
- [j27]Hans Vandierendonck, André Seznec:
Fairness Metrics for Multi-Threaded Processors. IEEE Comput. Archit. Lett. 10(1): 4-7 (2011) - [j26]Hans Vandierendonck, André Seznec:
Managing SMT resource usage through speculative instruction window weighting. ACM Trans. Archit. Code Optim. 8(3): 12:1-12:20 (2011) - [c53]Julien Dusser, André Seznec:
Decoupled zero-compressed memory. HiPEAC 2011: 77-86 - [c52]André Seznec:
Storage free confidence estimation for the TAGE branch predictor. HPCA 2011: 443-454 - [c51]Moinuddin K. Qureshi, André Seznec, Luis A. Lastras, Michele Franceschini:
Practical and secure PCM systems by online detection of malicious write streams. HPCA 2011: 478-489 - [c50]André Seznec:
A new case for the TAGE branch predictor. MICRO 2011: 117-127 - [r1]André Seznec:
Branch Predictors. Encyclopedia of Parallel Computing 2011: 176-182 - 2010
- [j25]André Seznec:
A Phase Change Memory as a Secure Main Memory. IEEE Comput. Archit. Lett. 9(1): 5-8 (2010) - [c49]Pierre Michaud, Yiannakis Sazeides, André Seznec:
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers 2010: 237-246 - [e3]André Seznec, Uri C. Weiser, Ronny Ronen:
37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7 [contents]
2000 – 2009
- 2009
- [j24]Hans Vandierendonck, André Seznec:
Fetch Gating Control through Speculative Instruction Window Weighting. Trans. High Perform. Embed. Archit. Compil. 2: 128-148 (2009) - [c48]Julien Dusser, Thomas Piquet, André Seznec:
Zero-content augmented caches. ICS 2009: 46-55 - [c47]Alin Suciu, Tudor Carean, André Seznec, Kinga Marton:
Parallel HAVEGE. PPAM (2) 2009: 145-154 - [e2]André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer:
High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings. Lecture Notes in Computer Science 5409, Springer 2009, ISBN 978-3-540-92989-5 [contents] - 2008
- [j23]Hans Vandierendonck, André Seznec:
Speculative return address stack management revisited. ACM Trans. Archit. Code Optim. 5(3): 15:1-15:20 (2008) - 2007
- [j22]André Seznec:
The L-TAGE Branch Predictor. J. Instr. Level Parallelism 9 (2007) - [j21]André Seznec:
The Idealistic GTL Predictor. J. Instr. Level Parallelism 9 (2007) - [j20]Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou:
A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. 4(2): 9 (2007) - [j19]Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam:
High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. 1: 5-29 (2007) - [c46]Thomas Piquet, Olivier Rochecouste, André Seznec:
Exploiting Single-Usage for Effective Memory Management. Asia-Pacific Computer Systems Architecture Conference 2007: 90-101 - [c45]Hans Vandierendonck, André Seznec:
Fetch Gating Control Through Speculative Instruction Window Weighting. HiPEAC 2007: 120-135 - 2006
- [j18]André Seznec, Pierre Michaud:
A case for (partially) TAgged GEometric history length branch prediction. J. Instr. Level Parallelism 8 (2006) - [j17]Olivier Rochecouste, Gilles Pokam, André Seznec:
A case for a complexity-effective, width-partitioned microarchitecture. ACM Trans. Archit. Code Optim. 3(3): 295-326 (2006) - 2005
- [j16]André Seznec:
Genesis of the O-GEHL Branch Predictor. J. Instr. Level Parallelism 7 (2005) - [j15]Julio César Hernández Castro, José María Sierra, André Seznec, Antonio Izquierdo, Arturo Ribagorda:
The strict avalanche criterion randomness test. Math. Comput. Simul. 68(1): 1-7 (2005) - [j14]Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec:
Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News 33(4): 80-91 (2005) - [j13]André Seznec, Roger Espasa:
Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers 54(7): 913-196 (2005) - [c44]André Seznec:
Analysis of the O-GEometric History Length Branch Predictor. ISCA 2005: 394-405 - 2004
- [j12]Romain Dolbeau, André Seznec:
CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors. J. Instr. Level Parallelism 6 (2004) - [j11]André Seznec:
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. IEEE Trans. Computers 53(7): 924-927 (2004) - [c43]Julio César Hernández Castro, André Seznec, Pedro Isasi:
On the design of state-of-the-art pseudorandom number generators by means of genetic programming. IEEE Congress on Evolutionary Computation 2004: 1510-1516 - [c42]Kemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci:
Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism. Euro-Par 2004: 506 - [c41]Julio César Hernández Castro, José María Sierra, André Seznec:
The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. ICCSA (1) 2004: 960-967 - [c40]Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin:
Speculative software management of datapath-width for energy optimization. LCTES 2004: 78-87 - [c39]Amaury Darsch, André Seznec:
IATO: A Flexible EPIC Simulation Environment. SBAC-PAD 2004: 58-65 - [e1]Paul Feautrier, James R. Goodman, André Seznec:
Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004. ACM 2004, ISBN 1-58113-839-3 [contents] - 2003
- [j10]André Seznec, Nicolas Sendrier:
HAVEGE: A user-level software heuristic for generating empirically strong random numbers. ACM Trans. Model. Comput. Simul. 13(4): 334-346 (2003) - [c38]André Seznec, Antony Fraboulet:
Effective ahead Pipelining of Instruction Block Address Generation. ISCA 2003: 241-252 - 2002
- [c37]Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec:
Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281-292 - [c36]André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. ISCA 2002: 295-306 - [c35]André Seznec, Eric Toullec, Olivier Rochecouste:
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. MICRO 2002: 383-394 - 2001
- [j9]Pierre Michaud, André Seznec, Stéphan Jourdan:
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. Int. J. Parallel Program. 29(1): 35-58 (2001) - [c34]Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec:
Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par 2001: 385 - [c33]Pierre Michaud, André Seznec:
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. HPCA 2001: 27-36 - [c32]Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec:
Boosting SMT Performance by Speculation Control. IPDPS 2001: 2 - 2000
- [j8]Erven Rohou, François Bodin, Christine Eisenbeis, André Seznec:
Handling Global Constraints in Compiler Strategy. Int. J. Parallel Program. 28(4): 325-345 (2000) - [c31]Thierry Lafage, André Seznec:
Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). Euro-Par 2000: 178-182
1990 – 1999
- 1999
- [c30]Pierre Michaud, André Seznec, Stéphan Jourdan:
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. IEEE PACT 1999: 2-10 - [c29]Michel Barreteau, François Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O'Boyle, Erven Rohou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff:
OCEANS - Optimising Compilers for Embedded Applications. Euro-Par 1999: 1171-1175 - [c28]Thierry Lafage, André Seznec, Erven Rohou, François Bodin:
Code Cloning Tracing: A "Pay per Trace" Approach. Euro-Par 1999: 1265-1268 - [c27]Sébastien Hily, André Seznec:
Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. HPCA 1999: 64-67 - 1998
- [c26]D. N. Truong, François Bodin, André Seznec:
Improving Cache Behavior of Dynamically Allocated Data Structures. IEEE PACT 1998: 322- - [c25]Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff:
OCEANS: Optimising Compilers for Embedded Applications. Euro-Par 1998: 1123-1130 - 1997
- [j7]André Seznec:
Decoupled Sectored Caches. IEEE Trans. Computers 46(2): 210-215 (1997) - [j6]François Bodin, André Seznec:
Skewed Associativity Improves Program Performance and Enhances Predictability. IEEE Trans. Computers 46(5): 530-544 (1997) - [c24]Bas Aarts, Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, André Seznec, Elena Stöhr, Marco Verhoeven, Harry A. G. Wijshoff:
OCEANS: Optimizing Compilers for Embedded Applications. Euro-Par 1997: 1351-1356 - [c23]Pierre Michaud, André Seznec, Richard Uhlig:
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. ISCA 1997: 292-303 - 1996
- [c22]Sébastien Hily, André Seznec:
Branch prediction and simultaneous multithreading. IEEE PACT 1996: 169-173 - [c21]André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud:
Multiple-Block Ahead Branch Predictors. ASPLOS 1996: 116-127 - [c20]André Seznec:
Don't Use the Page Number, But a Pointer To It. ISCA 1996: 104-113 - 1995
- [j5]André Seznec, Jacques Lenfant:
Odd Memory Systems: A New Approach. J. Parallel Distributed Comput. 26(2): 248-256 (1995) - [j4]Nathalie Drach, Alain Gefflaut, Philippe Joubert, André Seznec:
About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors. Parallel Process. Lett. 5: 475-487 (1995) - [c19]Nathalie Drach, André Seznec, Daniel Windheiser:
Direct-mapped versus set-associative pipelined caches. PACT 1995: 79-88 - [c18]André Seznec:
DASC Cache. HPCA 1995: 134-143 - [c17]François Bodin, André Seznec:
Skewed Associativity Enhances Performance Predictability. ISCA 1995: 265-274 - 1994
- [j3]André Seznec, Jacques Lenfant:
Interleaved Parallel Schemes. IEEE Trans. Parallel Distributed Syst. 5(12): 1329-1334 (1994) - [c16]André Seznec:
Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. ISCA 1994: 384-393 - 1993
- [c15]André Seznec:
About Set and Skewed Associativity on Second-Level Caches. ICCD 1993: 40-43 - [c14]Nathalie Drach, André Seznec:
Semi-Unified Caches. ICPP (1) 1993: 25-28 - [c13]André Seznec:
A Case for Two-Way Skewed-Associative Caches. ISCA 1993: 169-178 - [c12]André Seznec, Jacques Lenfant:
Odd Memory Systems May be Quite Interesting. ISCA 1993: 341-350 - [c11]Nathalie Drach, André Seznec:
MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines. MICRO 1993: 193-201 - [c10]André Seznec, François Bodin:
Skewed-associative Caches. PARLE 1993: 304-316 - 1992
- [c9]André Seznec, Jacques Lenfant:
Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers. ISCA 1992: 246-255 - [c8]André Seznec, Karl Courtel:
OPAC: A floating-point coprocessor dedicated to compute-bound kernels. ISCA 1992: 427 - [c7]André Seznec, Karl Courtel:
Controlling and sequencing a heavily pipelined floating-point operator. MICRO 1992: 111-114
1980 – 1989
- 1989
- [c6]Yvon Jégou, André Seznec:
A asynchronous buffering network for tightly coupled multiprocessors. ICS 1989: 331-340 - 1988
- [c5]André Seznec, Yvon Jégou:
Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache. ICS 1988: 611-620 - [c4]André Seznec, Yvon Jégou:
Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor. ISCA 1988: 393-400 - 1987
- [j2]André Seznec:
A New Interconnection Network for SIMD Computers: The Sigma Network. IEEE Trans. Computers 36(7): 794-801 (1987) - [c3]André Seznec, Yvon Jégou:
Optimizing Memory Throughput In a Tightly Coupled Multiprocessor. ICPP 1987: 344-346 - 1986
- [j1]Yvon Jégou, André Seznec:
Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. J. Parallel Distributed Comput. 3(4): 508-526 (1986) - [c2]Yvon Jégou, André Seznec:
Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. ICPP 1986: 487-494 - [c1]André Seznec:
An Efficient Routing Control Unit for the SIGMA Network E(4). ISCA 1986: 158-168
Coauthor Index
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