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ORCIDSIGARCH Computer Architecture News, Volume 33
Volume 33, Number 1 , March 2005
- David M. Chess:
Security in autonomic computing. 2-5 - Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Mrinmoy Ghosh:
Towards the issues in architectural support for protection of software execution. 6-15 - John Patrick McGregor, Ruby B. Lee:
Protecting cryptographic keys and computations via virtual secure coprocessing. 16-26 - Brian Rogers, Yan Solihin, Milos Prvulovic:
Memory predecryption: hiding the latency overhead of memory encryption. 27-33 - David A. Holland, Ada T. Lim, Margo I. Seltzer:
An architecture a day keeps the hacker away. 34-41 - Stelios Sidiroglou, Michael E. Locasto, Angelos D. Keromytis:
Hardware support for self-healing software services. 42-47 - Jedidiah R. Crandall, Frederic T. Chong:
A security assessment of the minos architecture. 48-57 - Matthew Burnside, Angelos D. Keromytis:
The case for crypto protocol awareness inside the OS kernel. 58-64 - Marc L. Corliss, E. Christopher Lewis, Amir Roth:
Using DISE to protect return addresses from attack. 65-72 - Dong Ye, David R. Kaeli:
A reliable return address stack: microarchitectural features to defeat stack smashing. 73-80 - Koji Inoue:
Energy-security tradeoff in a secure cache architecture against buffer overflow attacks. 81-89 - Derek Uluski, Micha Moffie, David R. Kaeli:
Characterizing antivirus workload execution. 90-98 - Monther Aldwairi, Thomas M. Conte
, Paul D. Franzon:
Configurable string matching hardware for speeding up intrusion detection. 99-107 - Milena Milenkovic, Aleksandar Milenkovic, Emil Jovanov:
Using instruction block signatures to counter code injection attacks. 108-117 - Youtao Zhang, Jun Yang, Yongjing Lin, Lan Gao:
Architectural support for protecting user privacy on trusted processors. 118-123 - Masaaki Shirase, Yasushi Hibino:
An architecture for elliptic curve cryptograph computation. 124-133 - Taeho Kgil, Laura Falk, Trevor N. Mudge:
ChipLock: support for secure microarchitectures. 134-143
- Magnus Ekman, Fredrik Warg, Jim Nilsson:
An in-depth look at computer performance growth. 144-147 - N. Venkateswaran, S. Balaji, V. Sridhar:
Fault tolerant bus architecture for deep submicron based processors. 148-155
- Mark Thorson:
Internet nuggets. 156-160
Volume 33, Number 2, May 2005
- 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA. IEEE Computer Society 2005, ISBN 978-0-7695-2270-8 [contents]
Volume 33, Number 3, June 2005
- Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Guests editor's introduction. 1-2 - Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin:
Energy aware memory architecture configuration. 3-9 - Hyo-Joong Suh, Sung Woo Chung:
DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency. 10-16 - Sami Yehia, Jean-Francois Collard, Olivier Temam:
Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios. 17-24 - Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa:
Locality analysis to control dynamically way-adaptable caches. 25-32 - Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori:
SH-X: an embedded processor core for consumer appliances. 33-40 - Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany:
Improving data cache performance with integrated use of split caches, victim cache and stream buffers. 41-48 - Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency. 49-56 - Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications. 57-62
- Bramha Allu, Wei Zhang:
Exploiting the replication cache to improve performance for multiple-issue microprocessors. 63-71
- Mark Thorson:
Internet nuggets. 72-74
Volume 33, Number 4 , November 2005
- Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). 4 - James Laudon:
Performance/Watt: the new server focus. 5-13 - John D. Davis, Cong Fu, James Laudon:
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors. 14-23 - Lisa R. Hsu, Ravishankar R. Iyer, Srihari Makineni, Steven K. Reinhardt, Donald Newell:
Exploring the cache design space for large scale CMPs. 24-33 - John D. Davis, Stephen E. Richardson, Charis Charitsis, Kunle Olukotun:
A chip prototyping substrate: the flexible architecture for simulation and testing (FAST). 34-43 - Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors:
Chip multi-processor scalability for single-threaded applications. 44-53 - Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi:
Hardware-modulated parallelism in chip multiprocessors. 54-63 - Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker:
Fast synchronization for chip multiprocessors. 64-69 - Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood:
Dynamically configurable shared CMP helper engines for improved performance. 70-79 - Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec:
Performance implications of single thread migration on a chip multi-core. 80-91
- Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood:
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. 92-99 - David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob:
DRAMsim: a memory system simulator. 100-107 - Barry Rountree, Robert Springer, David K. Lowenthal, Vincent W. Freeh:
Notes from HPPAC 2005. 108-112 - H. C. Wang, C. K. Yuen:
A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware. 113-120 - Nana B. Sam, Martin Burtscher:
Improving memory system performance with energy-efficient value speculation. 121-127
- Mark Thorson:
Internet Nuggets. 128-133
Volume 33, Number 5, December 2005
- David R. Kaeli, Robert Cohn:
Introduction to the special issue. 1-2 - Chunling Hu, John B. P. McCabe, Daniel A. Jiménez, Ulrich Kremer:
The Camino Compiler infrastructure. 3-8 - Martin Schulz, Dong H. Ahn, Andrew Bernat, Bronis R. de Supinski, Steven Y. Ko, Gregory L. Lee, Barry Rountree:
Scalable dynamic binary instrumentation for Blue Gene/L. 9-14 - Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo:
Dynamic binary control-flow errors detection. 15-20 - Micha Moffie, David R. Kaeli:
ASM: application security monitor. 21-26 - Qin Zhao, Rodric M. Rabbah, Weng-Fai Wong:
Dynamic memory optimization using pool allocation and prefetching. 27-32 - Xiaofeng Gao, Beth Simon, Allan Snavely:
ALITER: an asynchronous lightweight instrumentation tool for event recording. 33-38 - Collin McCurdy, Charles N. Fischer:
Using Pin as a memory reference generator for multiprocessor simulation. 39-44 - Heidi Pan, Krste Asanovic, Robert Cohn, Chi-Keung Luk:
Controlling program execution through binary instrumentation. 45-50 - Nikrouz Faroughi:
Profiling of parallel processing programs on shared memory multiprocessors using Simics. 51-56 - Naveen Kumar, Ramesh Peri:
Transparent debugging of dynamically instrumented programs. 57-62 - Laune C. Harris, Barton P. Miller:
Practical analysis of stripped binary code. 63-68 - Vijay Janapa Reddi, Dan Connors, Robert S. Cohn:
Persistence in dynamic code transformation systems. 69-74 - Ram Srinivasan, Olaf M. Lubeck:
MonteSim: a Monte Carlo performance model for in-order microachitectures. 75-80 - Michael Laurenzano, Beth Simon, Allan Snavely, Meghan Gunn:
Low cost trace-driven memory simulation using SimPoint. 81-86
- Mark Thorson:
Internet nuggets. 87-93
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