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ORCID49th MICRO 2016: Taipei, Taiwan
- 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-3508-3
- Margaret Martonosi:
Keynotes: Internet of Things: History and hype, technology and policy. 1-2 - Biswabandan Panda, André Seznec:
Dictionary sharing: An efficient cache compression scheme for compressed caches. 1:1-1:12 - Elvira Teran
, Zhe Wang, Daniel A. Jiménez:
Perceptron learning for reuse prediction. 2:1-2:12 - Prathmesh Kallurkar, Smruti R. Sarangi:
pTask: A smart prefetching scheme for OS intensive applications. 3:1-3:12 - Arthur Perais, Fernando A. Endo, André Seznec:
Register sharing for equality prediction. 4:1-4:12 - Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez:
Data-centric execution of speculative parallel programs. 5:1-5:13 - Alexandros Daglis, Dmitrii Ustiugov, Stanko Novakovic, Edouard Bugnion, Babak Falsafi, Boris Grot:
SABRes: Atomic object reads for in-memory rack-scale computing. 6:1-6:13 - Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, Doug Burger:
A cloud-scale acceleration architecture. 7:1-7:13 - Yang Hu, Tao Li:
Towards efficient server architecture for virtualized network function deployment: Implications and implementations. 8:1-8:12 - Renhai Chen, Zili Shao, Tao Li:
Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach. 9:1-9:12 - Yonatan Gottesman, Yoav Etsion:
NeSC: Self-virtualizing nested storage controller. 10:1-10:12 - Ahmed ElTantawy, Tor M. Aamodt:
MIMD synchronization on SIMT architectures. 11:1-11:14 - Li-Wen Chang, Izzat El Hajj, Christopher I. Rodrigues, Juan Gómez-Luna, Wen-mei W. Hwu:
Efficient kernel synthesis for performance portable programming. 12:1-12:13 - Izzat El Hajj, Juan Gómez-Luna, Cheng Li, Li-Wen Chang, Dejan S. Milojicic, Wen-mei W. Hwu:
KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism. 13:1-13:12 - Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang:
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. 14:1-14:12 - Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko, Samira Manabi Khan, Ashish Shrestha, Saugata Ghose, Adwait Jog, Phillip B. Gibbons, Onur Mutlu:
Zorua: A holistic approach to resource virtualization in GPUs. 15:1-15:14 - Muhammad Husni Santriaji, Henry Hoffmann:
GRAPE: Minimizing energy for GPU applications with performance requirements. 16:1-16:13 - Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit Mishra, Hadi Esmaeilzadeh:
From high-level deep neural models to FPGAs. 17:1-17:12 - Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Stephen W. Keckler:
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design. 18:1-18:13 - Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Andreas Moshovos:
Stripes: Bit-serial deep neural network computing. 19:1-19:12 - Shijin Zhang, Zidong Du, Lei Zhang, Huiying Lan, Shaoli Liu, Ling Li, Qi Guo, Tianshi Chen, Yunji Chen:
Cambricon-X: An accelerator for sparse neural networks. 20:1-20:12 - Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen:
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. 21:1-21:13 - Manoj Alwani, Han Chen, Michael Ferdman, Peter A. Milder:
Fused-layer CNN accelerators. 22:1-22:12 - Animesh Jain, Michael A. Laurenzano, Lingjia Tang, Jason Mars:
Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting. 23:1-23:12 - Stephen A. Zekany, Daniel Rings, Nathan Harada, Michael A. Laurenzano, Lingjia Tang, Jason Mars:
CrystalBall: Statically analyzing runtime behavior via deep sequence learning. 24:1-24:12 - Qingrui Liu, Changhee Jung, Dongyoon Lee, Devesh Tiwari:
Low-cost soft error resilience with unified data verification and fine-grained recovery for acoustic sensor based detection. 25:1-25:12 - Johnathan Alsop, Marc S. Orr, Bradford M. Beckmann, David A. Wood:
Lazy release consistency for GPUs. 26:1-26:13 - Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Improving energy efficiency of DRAM by exploiting half page row access. 27:1-27:12 - Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie:
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. 28:1-28:13 - Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie:
A unified memory network architecture for in-memory computing in commodity servers. 29:1-29:14 - Gwangsun Kim, Changhyun Kim, Jiyun Jeong, Mike Parker, John Kim:
Contention-based congestion management in large-scale networks. 30:1-30:13 - Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri:
Dynamic error mitigation in NoCs using intelligent prediction techniques. 31:1-31:12 - Shibo Wang, Engin Ipek:
Reducing data movement energy via online data clustering and encoding. 32:1-32:13 - Alberto Ros, Stefanos Kaxiras:
Racer: TSO consistency via race detection. 33:1-33:13 - Guowei Zhang, Virginia Chiu, Daniel Sánchez:
Exploiting semantic commutativity in hardware speculation. 34:1-34:12 - Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CANDY: Enabling coherent DRAM caches for multi-node systems. 35:1-35:13 - Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan:
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches. 36:1-36:12 - Mikhail Kazdagli, Vijay Janapa Reddi, Mohit Tiwari:
Quantifying and improving the efficiency of hardware-based mobile malware detectors. 37:1-37:13 - Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee:
PoisonIvy: Safe speculation for secure memory. 38:1-38:13 - Mengjia Yan, Yasser Shalabi, Josep Torrellas:
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay. 39:1-39:14 - Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh:
Jump over ASLR: Attacking branch predictors to bypass ASLR. 40:1-40:13 - Animesh Jain, Parker Hill, Shih-Chieh Lin, Muneeb Khan, Md. Enamul Haque, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars:
Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation. 41:1-41:13 - Radha Venkatagiri, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Sarita V. Adve:
Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency. 42:1-42:14 - Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, Aamer Jaleel:
The Bunker Cache for spatio-value approximation. 43:1-43:12 - Vaibhav Gogte, Aasheesh Kolli, Michael J. Cafarella, Loris D'Antoni, Thomas F. Wenisch:
HARE: Hardware accelerator for regular expressions. 44:1-44:12 - Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin:
The microarchitecture of a real-time robot motion planning accelerator. 45:1-45:12 - Tao Chen, G. Edward Suh:
Efficient data supply for hardware accelerators with prefetching and access/execute decoupling. 46:1-46:12 - Reza Yazdani, Albert Segura, José-María Arnau, Antonio González:
An ultra low-power hardware accelerator for automatic speech recognition. 47:1-47:12 - Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks:
Co-designing accelerators and SoC interfaces using gem5-Aladdin. 48:1-48:12 - Amirali Sharifian, Snehasish Kumar, Apala Guha, Arrvindh Shriraman:
Chainsaw: Von-neumann accelerators to leverage fused instruction chains. 49:1-49:14 - Hadi Asghari Moghaddam, Young Hoon Son, Jung Ho Ahn, Nam Sung Kim:
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems. 50:1-50:13 - Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler:
A patch memory system for image processing and computer vision. 51:1-51:13 - Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Evaluating programmable architectures for imaging and vision applications. 52:1-52:13 - Kaige Yan, Xingyao Zhang, Jingweijia Tan, Xin Fu:
Redefining QoS and customizing the power management policy to satisfy individual mobile users. 53:1-53:12 - Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas:
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. 54:1-54:12 - Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi:
Ti-states: Processor power management in the temperature inversion region. 55:1-55:13 - Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Satish, Margaret Martonosi:
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics. 56:1-56:13 - Xulong Tang, Mahmut T. Kandemir, Praveen Yedlapalli, Jagadish Kotra:
Improving bank-level parallelism for irregular applications. 57:1-57:12 - Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali G. Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, Thomas F. Wenisch:
Delegated persist ordering. 58:1-58:13 - Nader Sehatbakhsh, Alireza Nazari, Alenka G. Zajic, Milos Prvulovic:
Spectral profiling: Observer-effect-free profiling by monitoring EM emanations. 59:1-59:11 - Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti:
Path confidence based lookahead prefetching. 60:1-60:12 - Milad Hashemi, Onur Mutlu, Yale N. Patt:
Continuous runahead: Transparent hardware acceleration for memory intensive workloads. 61:1-61:12
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