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Siddharth Rao
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2020 – today
- 2024
- [c17]Sicong Yuan, Mohammad Amin Yaldagard
, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui:
Design-for-Test for Intermittent Faults in STT-MRAMs. ETS 2024: 1-6 - 2023
- [c16]Ahmed Aouichi, Sicong Yuan, Moritz Fieback
, Siddharth Rao, Woojin Kim, Erik Jan Marinissen, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui:
Device Aware Diagnosis for Unique Defects in STT-MRAMs. ATS 2023: 1-6 - [c15]M. Gupta, Siddharth Rao, Gouri Sankar Kar, S. Couet:
Magnetic Domain Wall Memory: A DTCO study for Memory Applications. ESSDERC 2023: 41-44 - [c14]Siddharth Rao, Kaiming Cai, Giacomo Talmelli, Nathali Franchina-Vergel, Ward Janssens, Hubert Hody, Farrukh Yasin, Kurt Wostyn, Sebastien Couet:
Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications. IMW 2023: 1-4 - [c13]Simon Van Beek, Kaiming Cai, Kaiquan Fan, Giacomo Talmelli, Anna Trovato, Nico Jossart, Siddharth Rao, Adrian Vaisman Chasin, Sebastien Couet:
MTJ degradation in multi-pillar SOT-MRAM with selective writing. IRPS 2023: 1-7 - 2022
- [j3]Lizhou Wu
, Siddharth Rao
, Mottaqiallah Taouil
, Erik Jan Marinissen
, Gouri Sankar Kar, Said Hamdioui
:
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. IEEE Trans. Computers 71(9): 2219-2233 (2022) - [j2]Lizhou Wu
, Siddharth Rao
, Mottaqiallah Taouil
, Erik Jan Marinissen
, Gouri Sankar Kar, Said Hamdioui
:
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4991-5004 (2022) - [c12]Simon Van Beek, Kaiming Cai
, Siddharth Rao
, Ganesh Jayakumar, Sebastien Couet, Nico Jossart, Adrian Vaisman Chasin, Gouri Sankar Kar:
MTJ degradation in SOT-MRAM by self-heating-induced diffusion. IRPS 2022: 4 - [c11]Kaiming Cai, Simon Van Beek, Siddharth Rao, K. Fan
, M. Gupta, V. D. Nguyen, Ganesh Jayakumar, Giacomo Talmelli, S. Couet, Gouri Sankar Kar:
Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories. VLSI Technology and Circuits 2022: 375-376 - [c10]Anteneh Gebregiorgis, Lizhou Wu, Christopher Münch, Siddharth Rao
, Mehdi B. Tahoori, Said Hamdioui:
Special Session: STT-MRAMs: Technology, Design and Test. VTS 2022: 1-10 - 2021
- [j1]Lizhou Wu
, Siddharth Rao
, Mottaqiallah Taouil
, Guilherme Cardoso Medeiros, Moritz Fieback
, Erik Jan Marinissen
, Gouri Sankar Kar, Said Hamdioui
:
Defect and Fault Modeling Framework for STT-MRAM Testing. IEEE Trans. Emerg. Top. Comput. 9(2): 707-723 (2021) - [c9]Lizhou Wu, Siddharth Rao
, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. DATE 2021: 1717-1722 - [c8]Simon Van Beek, Siddharth Rao
, Shreya Kundu, Woojin Kim, Barry J. O'Sullivan, Stefan Cosemans, Farrukh Yasin, Robert Carpenter, Sebastien Couet
, Shamin H. Sharifi, Nico Jossart, Davide Crotti, Gouri Sankar Kar:
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS 2021: 1-5 - [c7]Lizhou Wu, Siddharth Rao
, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. ITC 2021: 143-152 - 2020
- [c6]Lizhou Wu, Siddharth Rao
, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Impact of Magnetic Coupling and Density on STT-MRAM Performance. DATE 2020: 1211-1216 - [c5]Lizhou Wu, Siddharth Rao
, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. ITC 2020: 1-10 - [i2]Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui:
Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. CoRR abs/2001.05463 (2020) - [i1]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Impact of Magnetic Coupling and Density on STT-MRAM Performance. CoRR abs/2011.11349 (2020)
2010 – 2019
- 2019
- [c4]Lizhou Wu, Siddharth Rao
, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen
, Farrukh Yasin, Sebastien Couet
, Said Hamdioui, Gouri Sankar Kar:
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. ETS 2019: 1-6 - [c3]Moritz Fieback
, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao
, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui:
Device-Aware Test: A New Test Approach Towards DPPB Level. ITC 2019: 1-10 - 2018
- [c2]Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao
, Erik Jan Marinissen
, Said Hamdioui:
Electrical Modeling of STT-MRAM Defects. ITC 2018: 1-10 - 2017
- [c1]Manu Komalan, Sushil Sakhare, Trong Huynh Bao, Siddharth Rao
, Woojin Kim, Christian Tenllado, José Ignacio Gómez
, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor:
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. ISCAS 2017: 1-4
Coauthor Index
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last updated on 2024-08-05 21:17 CEST by the dblp team
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