Volume 10, Number 1, January 1991
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journals/tcad/BartlettBR91
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Giovanni De Micheli :
Synchronous logic synthesis: algorithms for cycle-time minimization.
63-73
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journals/tcad/Camposano91
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Randal E. Bryant :
Formal verification of memory circuits by switch-level simulation.
94-102
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journals/tcad/YoungTWTA91
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Niraj K. Jha :
Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes.
136-143
Volume 10, Number 2, February 1991
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journals/tcad/MasudaMISA91
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journals/tcad/FeldmannNDR91
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Peter M. Maurer :
Scheduling blocks of hierarchical compiled simulation of combinational circuits.
184-192
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Anthony Vannelli :
An adaptation of the interior point method for solving the global routing problem.
193-203
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journals/tcad/IvanovSADGW91
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Volume 10, Number 3, March 1991
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journals/tcad/Andersson91
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Dan Adler :
Switch-level simulation using dynamic graph algorithms.
346-355
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journals/tcad/KleinhansSJA91
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journals/tcad/YanilmazE91
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Charles H. Stapper :
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement.
399-406
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Volume 10, Number 4, April 1991
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journals/tcad/KeutzerMS91
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journals/tcad/ShungJRWSRLATHRB91 C. Bernard Shung ,
Rajeev Jain ,
Ken Rimey ,
Edward Wang ,
Mani B. Srivastava ,
Brian C. Richards ,
Erik Lettang ,
Syed Khalid Azim ,
Lars E. Thon ,
Paul N. Hilfinger ,
Jan M. Rabaey ,
Robert W. Brodersen :
An integrated CAD system for algorithm-specific IC design.
447-463
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journals/tcad/CohoonHMR91
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journals/tcad/AllegrettoNB91
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Gerd Krüger :
A tool for hierarchical test generation.
519-524
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journals/tcad/FavalliOR91
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Volume 10, Number 5, May 1991
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journals/tcad/BelkhaleB91
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journals/tcad/OdanakaHOMU91
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journals/tcad/FairGJKRRS91
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journals/tcad/AccianiCD91
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Volume 10, Number 6, June 1991
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David M. Lewis :
A hierarchical compiled code event-driven logic simulator.
726-737
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journals/tcad/HeistermanL91
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journals/tcad/ChaudharyR91
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journals/tcad/CarlsonCS91
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journals/tcad/HiraiTISEHN91
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Volume 10, Number 7, July 1991
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journals/tcad/VisweswariahR91
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journals/tcad/KravitzBR91
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journals/tcad/GuggenbuhlMS91
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Larry G. Jones :
Fast batch incremental netlist compilation hierarchical schematics.
922-931
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journals/tcad/ChakravartyHR91
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Volume 10, Number 8, August 1991
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Jason Cong ,
C. L. Liu :
On the k-layer planar subset and topological via minimization problems.
972-981
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journals/tcad/ShiraishiSF91
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journals/tcad/Abdel-MalekH91
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journals/tcad/StrojwasD91
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C. Leonard Berman :
Circuit width, register allocation, and ordered binary decision diagrams.
1059-1066
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Giuseppe Caruso :
Near optimal factorization of Boolean functions.
1072-1078
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Pak K. Chan :
Comments on `Asymptotic waveform evaluation for timing analysis'.
1078-1079
Volume 10, Number 9, September 1991
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journals/tcad/GuerrieriTGN91
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T. Thurgate :
Segment-based etch algorithm and modeling.
1101-1109
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Mark E. Law :
Parameters for point-defect diffusion and recombination.
1125-1131
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journals/tcad/CiampoliniPB91
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Mark R. Simpson :
PRIDE: an integrated design environment for semiconductor device simulation.
1163-1174
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journals/tcad/GardnerLR91
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Volume 10, Number 10, October 1991
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journals/tcad/VenturiSBQJR91
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Volume 10, Number 11, November 1991
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journals/tcad/Bergamaschi91
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Jason Cong :
Pin assignment with global routing for general cell designs.
1401-1412
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Craig MacInnes :
The use of small pivot perturbation in circuit analysis.
1441-1446
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Volume 10, Number 12, December 1991
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Srinivas Devadas :
Optimizing interacting finite state machines using sequential don't cares.
1473-1484
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journals/tcad/BoothroydTS91
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journals/tcad/Drusinsky-Yoresh91 Doron Drusinsky-Yoresh :
A state assignment procedure for single-block implementation of state charts.
1569-1576
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journals/tcad/Drusinsky-Yoresh91a
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Yie He ,
Guoxiang Cao :
A generalized Scharfetter-Gummel method to eliminate crosswind effects [semiconduction device modeling].
1579-1582
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journals/tcad/TakefujiLC91