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ORCIDIEEE Design & Test of Computers, Volume 2
Volume 2, Number 1, February 1985
- John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor:
The Magic VLSI Layout System. 19-30 - Todd J. Wagner:
Hierarchical Layout Verification. 31-37 - Sunil K. Jain, Vishwani D. Agrawal:
Statistical Fault Analysis. 38-44 - Louis I. Steinberg, Tom M. Mitchell:
The Redesign System: A Knowledge-Based Approach to VLSI CAD. 45-54 - Karl J. Lieberherr:
Toward a Standard Hardware Description Language. 55-62 - John D. Crawford:
EDIF: A Mechanism for the Exchange of Design Information. 63-69 - J. Daniel Nash:
New Products Design. 82-86 - Conrad Zagwyn:
New Products Test. 87-91 - Robert E. Anderson:
Book Reviews. 94-95
Volume 2, Number 2, April 1985
- Edward J. McCluskey:
Built-In Self-Test Techniques. 21-28 - Edward J. McCluskey:
Built-In Self-Test Structures. 29-36 - Robert P. Treuer, Hideo Fujiwara, Vinod K. Agarwal:
Implementing a Built-In Self-Test PLA Design. 37-48 - Richard J. Illman:
Self-Tested Data Flow Logic: A New Approach. 50-58 - Thomas W. Williams:
Test Length in a Self-Testing Environment. 59-63 - R. Gary Daniels, William C. Bruce:
Built-In Self-Test Trends in Motorola Microprocessors. 64-71 - Carolyn E. Tajnai:
Fred Terman, the Father of Silicon Valley. 75-81 - Donald L. Lacy, Lawrence A. Drenan:
Implementing and Managing a CAD System Based on Vendor-Supplied Tools. 82-87 - Conrad Zagwyn:
New Products Test. 96-100 - J. Daniel Nash:
New Products Design. 101-103 - A. Richard Newton, Donald O. Pederson, Alberto L. Sangiovanni-Vincentelli
:
Design Aids for VLSI: A Perspective Revisited. 106-115 - Robert E. Anderson:
Book Reviews. 118-119
Volume 2, Number 3, June 1985
- Gordon H. Bowers Jr., Bruce G. Pratt:
Low-Cost Testers: Are They Really Low Cost? 20-28 - Anthony P. van den Heuvel, Noshir F. Khory:
A Basis for Setting Burn-in Yield Criteria. 29-34 - John R. Day:
A Fault-Driven, Comprehensive Redundancy Algorithm. 35-44 - Dean Bandes:
Exploratory Data Analysis for Semiconductor Manufacturing. 45-55 - Douglas K. Shirachi:
Codec Testing Using Synchronized Analog And Digital Signals. 56-63 - Thomas G. Szymanski, Christopher J. Van Wyk:
Goalie: A Space Efficient System for VLSI Artwork Analysis. 64-72 - Conrad Zagwyn:
New Products Test. 101-103 - J. Daniel Nash:
New Products Design. 104-107 - Robert E. Anderson:
Book Reviews. 110
Volume 2, Number 4, August 1985
- Aart J. de Geus, William W. Cohen:
A Rule-Based System for Optimizing Combinational Logic. 22-32 - Ted J. Kowalski, David J. Geiger, Wayne H. Wolf, Wolfgang Fichtner:
The VLSI Design Automation Assistant: From Algorithms to Silicon. 33-43 - Robert A. Mueller, Joseph Varghese:
Knowledge-Based Code Selection Methods in Retargetable Microcode Synthesis. 44-55 - Magdy S. Abadir, Melvin A. Breuer:
A Knowledge-Based System for Designing Testable VLSI Chips. 56-68 - A. Jesse Wilkinson:
MIND: An inside Look at an Expert System for Electronic Diagnosis. 69-77 - Tariq Samad, Stephen W. Director:
Natural-Language Interface for CAD: A First Step. 78-86 - J. Daniel Nash:
New Products Design. 93-96 - Conrad Zagwyn:
New Products Test. 97-99
Volume 2, Number 5, October 1985
- Osamu Karatsu, Tamio Hoshino, Makoto Endo, Hitoshi Kitazawa, Tohru Adachi, Kazuhiro Ueda:
An Integrated Design Automation System for VLSI Circuits. 17-26 - Takao Uehara:
A Knowledge-Based Logic Design System. 27-34 - Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai:
LORES-2: A Logic Reorganization System. 35-42 - Tokinori Kozawa, Hidekazu Terai:
Research in Design Automation for VLSI Layout. 43-53 - Shigehiro Funatsu, Masato Kawai:
An Automatic Test-Generation System for Large Digital Circuits. 54-60 - Nobuhiko Koike, Kenji Ohmori, Tohru Sasaki:
HAL: A High-Speed Logic Simulation Machine. 61-73 - Norio Kuji, Teruo Tamama, Takao Yano:
A Fully-Automated Electron Beam Test System for VLSI Circuits. 74-82 - Tohru Kazamaki:
Milestones of New-Generation ATE. 83-89 - J. Daniel Nash:
New Products Design. 112-115 - Conrad Zagwyn:
New Products Test. 116-117 - Robert E. Anderson:
Book Reviews. 125-127
Volume 2, Number 6, December 1985
- John Paul Shen, Wojciech Maly, F. Joel Ferguson:
Inductive Fault Analysis of MOS Integrated Circuits. 13-26 - Peter Odryna, Andrzej J. Strojwas:
PROD: A VLSI Fault Diagnosis System. 27-35 - Kofi E. Torku, Dave A. Kiesling:
Noise Problems in Testing VLSI Hardware. 36-43 - Tim Moore, Stephen Garner:
Autoprobing on the L200 Functional Tester. 44-49 - David F. Farnholtz:
Operational Life Testing of Electronic Components. 50-56 - Wayne Ponik:
Teradyne's J967 VLSI Test System: Getting VLSI to the Market on Time. 57-62
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