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Todd J. Wagner

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1980 – 1989

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1985
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Todd J. Wagner:
Hierarchical Layout Verification. IEEE Des. Test 2(1): 31-37 (1985)
1984
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Todd J. Wagner:
Hierarchical layout verification. DAC 1984: 484-489

1970 – 1979

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1977
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Todd J. Wagner:
Hardware verification. Stanford University, USA, 1977
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Todd J. Wagner:
Verification of hardware designs thru symbolic manipulation. Design Automation and Microprocessors 1977: 50-53

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