SoCC 2010:
Las Vegas,
NV,
USA
Thomas Büchner, Ramalingam Sridhar, Andrew Marshall, Norbert Schuhmann (Eds.):
Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings.
IEEE 2010, ISBN 978-1-4244-6682-5
SoC Power Optimization Techniques
Analog 1
- Oliver E. Gysel, Paul J. Hurst, Stephen H. Lewis:
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks.
33-38
- Minah Kwon, Dahsom Kim, Daeyun Kim, Junho Moon, Minkyu Song:
A digitally self-calibrated low-noise 7-bit folding A/D converter.
39-43
- Jong-Kwan Woo, Hyunjoong Lee, SungHo Ahn, Suhwan Kim:
A high-resolution and fast-conversion readout circuit for differential capacitive sensors.
44-47
- Hongjiang Song, Jianan Song, Aritra Dey, Yan Song:
Jitter transfer function model and VLSI jitter filter circuits.
48-51
Embedded Tutorial
Low Power SoC Circuits
Analog 2
- Dongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung:
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.
79-82
- Sang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim, Jae-Youl Lee, Yoon-Kyung Choi, Myunghee Lee:
A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS.
84-87
- Jae-Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang:
A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2.
88-91
Embedded Tutorial
- Kaijian Shi:
Low-power SOC implementation: What you need to know.
95
Multimedia Processing
- Ning Ma, Zhonghai Lu, Zhibo Pang, Li-Rong Zheng:
System-level exploration of mesh-based NoC architectures for multimedia applications.
99-104
- Soonwoo Choi, Jason J. K. Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae:
A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor.
105-108
- Xin Zhao, Ying Yi, Ahmet T. Erdogan, Tughrul Arslan:
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras.
109-112
- Markus Holzer, Ruben Bartholomä, Thomas Greiner, Wolfgang Rosenstiel:
Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operations.
113-118
System Level Design Methodologies
Design
System Level Design Methodologies
- Siwat Saibua, Po-Yu Kuo, Dian Zhou, Ming-e Jing:
A Folding Strategy for SAT solvers based on Shannon's expansion theorem.
177-181
- Dan Liu, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang:
TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures.
182-187
- Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou:
Expandable MDC-based FFT architecture and its generator for high-performance applications.
188-192
- Thomas Uhle, Karsten Einwich:
A SystemCAMS extension for the simulation of non-linear circuits.
193-198
- Moazzam Fareed Niazi, Tiberiu Seceleanu, Hannu Tenhunen:
An automated control code generation approach for the SegBus platform.
199-204
Luncheon
- P. R. Mukund:
From Film to Silicon: The Migration of Document Archiving Technology.
205
Low Power Design
- Tien-Hung Lin, Po-Tsang Huang, Wei Hwang:
Power noise suppression technique using active decoupling capacitor for TSV 3D integration.
209-212
- Tung-Yeh Wu, Sriram Sambamurthy, Jacob A. Abraham:
Estimation of maximum application-level power supply noise.
213-218
- Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen:
Simultaneous voltage island generation and floorplanning.
219-223
- Rahul Singh, AhReum Kim, Suhwan Kim:
Footer voltage feedforward domino technique for wide fan-in dynamic logic.
224-229
- Ankitchandra Shah, Hamid Mahmoodi:
Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits.
230-235
- Yu-Jen Huang, Yun-Chao You, Jin-Fu Li:
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs.
236-240
Reconfigurable Systems
- Yuji Aoyama, Minoru Watanabe:
Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array.
243-247
- Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.
248-253
- Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hongying Meng:
Binary object recognition system on FPGA with bSOM.
254-259
- Naifeng Jing, Weifeng He, Zhigang Mao:
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.
260-265
- Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija:
Design of a link-controller architecture for multiple serial link protocols.
266-271
- Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
High-Performance random data lookup for network processing.
272-277
Poster Session
Analog and Mixed Signals
Reconfigurable and Programmable Circuits and Systems,
FPGAs
Embedded Systems,
Multi Core,
and Embedded Memory
Low Power
- Jinhui Wang, Na Gong, Wuchen Wu, Ligang Hou:
Fan-in sensitive low power dynamic circuits performance statistical characterization.
321-325
- Senthil Jayapal, Jan Stuijt, Jos Huisken, Yiannos Manoli:
Energy efficient computation with self-adaptive single-ended body bias.
326-329
- Osman Kubilay Ekekon, Samed Maltabas, Martin Margala, Ugur Çilingiroglu:
Power minimization methodology for VCTL topologies.
330-333
- Kyung Ki Kim, Haiqing Nan, Ken Choi:
Hybrid MOSFET/CNFET based power gating structure.
334-338
Verification
Multimedia Processing
Network on Chip and Interconnect
- Fangfa Fu, Siyue Sun, Xin'an Hu, Junjie Song, Jinxiang Wang, Mingyan Yu:
MMPI: A flexible and efficient multiprocessor message passing interface for NoC-based MPSoC.
359-362
- Rana Farah, Haidar Harmanani:
A method for efficient NoC test scheduling using deterministic routing.
363-366
- Everton Carara, Fernando Moraes:
Flow oriented routing for NOCS.
367-370
- Marek Tudruj, Lukasz Masko:
A globally-interconnected modular CMP system with communication on the fly.
371-374
- Yiou Chen, Jianhao Hu, Gengsheng Chen, Xiang Ling:
Energy and delay-aware mapping for real-time digital processing system on network on chip platforms.
375-378
- Kameswar Rao Vaddina, Tamoghna Mitra, Pasi Liljeberg, Juha Plosila:
Thermal modelling of 3D multicore systems in a flip-chip package.
379-383
- Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu:
Efficient multicasting scheme for irregular mesh-based NoCs.
384-387
System Level Design Methodology
Plenary Session
Embedded Tutorial
- Lech Józwiak:
Quality-driven SoC architecture synthesis for embedded applications.
425-426
Network on Chip 1
- Wen-Chung Tsai, Ying-Cherng Lan, Sao-Jie Chen, Yu Hen Hu:
DyML: Dynamic Multi-Level flow control for Networks on Chip.
429-434
- Jon Nafziger, Annie Avakian, Ranga Vemuri:
A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems.
435-440
- Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang:
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.
441-446
- Ankit More, Baris Taskin:
Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC.
447-452
Embedded Memory and Systems 1
- Bai Na, Xuan Chen, Yang Jun, Longxin Shi:
A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme.
455-460
- Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan:
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.
461-466
- Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
467-472
- Hamed Salah, Hazem A. Ahmed, Tallal Elshabrawy, Hossam A. H. Fahmy:
Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder.
473-478
Network on Chip 2
- Liang Guang, Ethiopia Nigussie, Hannu Tenhunen:
Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip.
481-486
- Sujay Deb, Kevin Chang, Amlan Ganguly, Partha Pratim Pande:
Comparative performance evaluation of wireless and optical NoC architectures.
487-492
- Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.
493-498
- Mohamed A. Abd El-Ghany, Gursharan Reehal, Darek Korzec, Mohammed Ismail:
Power analysis for Asynchronous CLICHÉ Network-on-Chip.
499-504
Embedded Memory and Systems 2
- Satish Raghunath, Naveen Davanam, Lakshmi Deepika Bobbala, Byeong Kil Lee:
Way-load balancing scheme for mobile cache LRU replacement.
507-512
- Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli:
Exploiting large on-chip memory space through data recomputation.
513-518
- Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto:
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.
519-524
Last update Fri May 25 08:40:29 2012
CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page