ITC 1988:
Washington, D.C., USASession 1:
Plenary:
Keynote Address and Invited Speakers
Keynote Speaker
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Invited Speakers
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Lutz P. Henckels :
Scan Path and Beyond : The Road to Improved ASIC Testability.
2
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conf/itc/Sangiovanni-Vincentelli88
Session 2:
New Advances in Test Hardware
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Session 3:
Board Test:
New Problems and Applications
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Session 4:
Testing Microprocessors:
A Life Cycle's Work
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Hans Peter Klug :
Microprocessor Testing by Instruction Sequences Derived from Random Patterns.
73-80
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Janusz Sosnowski :
Detection of Control Flow Errors Using Signature and Checking Instructions.
81-88
Session 5:
Software and Hardware Approaches to Fault Simulation
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Session 6:
Ultimate:
The Wave of the Future
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Session 7:
Boundary Scan and Test Bus
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Matthias Gruetzner :
Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test Methodology.
146-152
Session 8:
Test Features of Today's Microprocessors
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Luis A. Bonet :
Testability Features of a 32 Kbps ADPCM Transcoder.
161-171
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Session 9:
Panel Session:
What ist the Path to Fast Fault Simulation?
Session 10:
Panel Session:
Componenent ATE Timing Accuracy Specifications:
Can We Standardize?
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Marc Mydill :
Standardization of ATE Timing Accuracy Specifications.
193-194
Session 11:
Panel Sesssion:
Testability Standards
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Pete Fleming :
Semiconductor Perspective on Test Standards.
197-198
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Charles R. Kime :
Impact of Testability Standards on University Research and Instruction.
199-200
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David J. Richards :
Value of Testability Standards in Testing Commercial Products.
201-202
Session 13:
Panel Session Test Education:
Linking Theory and Practice
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Session 14:
High-Level Test Generation
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Session 15:
Weighted Pseudorandom Pattern Genereation for BIST
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Fardad Siavoshi :
WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test.
256-262
Session 16:
RAM Design for Test
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Pinaki Mazumder :
An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory.
279-288
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Steve Grennan :
Application of a Commercial Data Base Management System to Memory Device Test Program Generation and Debugging.
289-294
Session 17:
Quality, Yield, and the Cost of Test
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Session 19:
Design and Evaluation of Signature Analysis Based BIST
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Session 20:
SRAM Test Methods
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Session 21:
Reliability Test Detection Strategies
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Session 22:
Board Test Technology and Practice
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John Arena :
Evaluating the Limitations of High-Speed Board Testers.
411-420
Session 23:
BIST Control and Test Scheduling
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Session 24:
CAE and Workstations I
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John Ivie :
A High Level Approach to Integrating Design and Test.
452-459
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Cristopher Merritt :
A Strategy for Generating Functional Tests from Device Simulations.
466-474
Session 25:
Realistic Defects and Their Impact on Shipped Quality
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Session 26:
Panel Session:
High Frequency DUT-Tester Interconnection Problems
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Session 27:
Implementation and Analysis of BIST
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Session 28:
CAE and Workstations II
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Session 29:
Advances in Ffault Simulation and Fault Modeling
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Session 30:
High-Speed Probing
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Session 31:
Design for Testability I
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Session 32:
Testing ASICs
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Session 33:
Test Generation:
Techniques
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Session 34:
Novel Test Techniques Using Optics
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Session 35:
Design for Testability II
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Session 36:
Mixed-Signal Testing
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John L. Russo :
Flexible Deep Memory Architecture Aids Program Development.
752-754
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Session 37:
Test Generation:
Algorithms
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Session 38:
Process Improvement:
Data in Action
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Session 39:
Analog Design for Testability
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Session 40:
Test Generation:
Delay Testing
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Session 41:
Systems Test I
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Session 42:
E-Beam Concepts
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Session 43:
Concurrent BIST Techniques
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Session 44:
VLSI Processor Test:
Techniques and Technology
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Kenneth R. Stuchlik :
Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL).
948-957
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Session 45:
Systems Test II
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Bulent I. Dervisoglu :
Using Scan Technology for Debug and Diagnostics in a Workstation Environment.
976-986
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Poster Session
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conf/itc/HallenbeckkKVW88 export record as
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Cuong Bui :
Testability Using Random Access Test Register.
994-995
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Peter N. Marinos :
The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) Resource.
998
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data released under the ODC-BY 1.0 license
