Hai Zhou , Enrico Macii , Zhiyuan Yan , Yehia Massoud (Eds.):
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007.
ACM 2007, ISBN 978-1-59593-605-9
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Philippe Magarshack :
Design challenges in 45nm and below: DFM, low-power and design for reliability.
1
Architecture and memory
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Sangyeun Cho :
I-cache multi-banking and vertical interleaving.
14-19
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Timing and power analysis
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Test and reliability
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Device, interconnect, and power optimization for nano-CMOS
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conf/glvlsi/GiorgettiSST07 export record as
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conf/glvlsi/PapaefstathiouKC07
Emerging technologies
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Low power architecture and interconnect
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conf/glvlsi/FernandezRB07 export record as
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A. Robinson ,
Jim D. Garside :
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.
138-143
Poster session 1
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conf/glvlsi/SakiyamaMPV07 export record as
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conf/glvlsi/RaghavendraA07 export record as
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Dariusz Kania :
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS.
152-155
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Circuits and logic
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Kambiz Rahimi :
Minimizing peak power in synchronous logic circuits.
247-252
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Cosmin Popa :
Linearized CMOS active resistor independent on the bulk effect.
253-256
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conf/glvlsi/ZieglerDKQS07
Emerging technologies for low power design
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Digital synthesis
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conf/glvlsi/CartaAVAMRBM07 export record as
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Embedded tutorial
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ASIP/ASIC
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Hai Lin ,
Yunsi Fei :
Utilizing custom registers in application-specific instruction set processors for register spills elimination.
323-328
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conf/glvlsi/MohammadZadehNHG07 export record as
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conf/glvlsi/DassattiZNM07 export record as
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System level design
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conf/glvlsi/FarahaniKFS07 export record as
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CMOS & logic applications optimization and techniques
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conf/glvlsi/BernardiGMRS07
Verification techniques
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Optimization and verification
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Poster session 2
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conf/glvlsi/NakatakeKTS07 export record as
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Koji Ohashi ,
Mineo Kaneko :
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.
481-484
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conf/glvlsi/GentiliniSD07 export record as
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Arithmetic and coding
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Chichyang Chen ,
Paul Chow :
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.
540-545
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Dong-Ho Lee ,
Jong-Soo Oh :
Multi-segment GF (2m 546-551
Routing and buffer insertion
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Power estimation and modeling
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