17. ACM Great Lakes Symposium on VLSI 2007: Stresa, Lago Maggiore, Italy

Architecture and memory

Timing and power analysis

Test and reliability

Device, interconnect, and power optimization for nano-CMOS

Emerging technologies

Low power architecture and interconnect

Poster session 1

Circuits and logic

Emerging technologies for low power design

Digital synthesis

Embedded tutorial

ASIP/ASIC

System level design

CMOS & logic applications optimization and techniques

Verification techniques

Optimization and verification

Poster session 2

Arithmetic and coding

Routing and buffer insertion

Power estimation and modeling

maintained by Schloss Dagstuhl LZI at University of Trier