19. FPL 2009: Prague, Czech Republic

Keynotes

• Jason Cong:
  Customizable domain-specific computing. 1
  
• Peter Athanas:
  In search of agile hardware. 2
  
• Jonathan Rose:
  The evolution of architecture exploration of programmable devices. 3
  
• Vaughn Betz:
  FPGA challenges and opportunities at 40nm and beyond. 4
  
• Peter Alfke:
  Virtex-6 and Spartan-6, plus a look into the future. 5
  

Threads, MPI, Multi-CPU Systems

• Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano:
  MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. 6-11
  
• Shanyuan Gao, Andrew G. Schmidt, Ron Sass:
  Hardware implementation of MPI_Barrier on an FPGA cluster. 12-17
  
• Martin Labrecque, J. Gregory Steffan:
  Fast critical sections via thread scheduling for FPGA-based multithreaded processors. 18-25
  

Practical Applications

• Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly:
  A biophysically accurate floating point somatic neuroprocessor. 26-31
  
• Clément Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCun:
  CNP: An FPGA-based processor for Convolutional Networks. 32-37
  
• Brian H. Pratt, Michael J. Wirthlin, Michael P. Caffrey, Paul S. Graham, Keith Morgan:
  Noise impact of single-event upsets on an FPGA-based digital filter. 38-43
  

Acceleration

• Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels:
  Compiler assisted runtime task scheduling on a reconfigurable computer. 44-50
  
• Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
  Data parallel FPGA workloads: Software versus hardware. 51-58
  
• Florent de Dinechin, Cristian Klein, Bogdan Pasca:
  Generating high-performance custom floating-point pipelines. 59-64
  

GPU, CPU, FPGA Register Allocation

• Nachiket Kapre, André DeHon:
  Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. 65-72
  
• Qiwei Jin, David B. Thomas, Wayne Luk:
  Exploring reconfigurable architectures for explicit finite difference option pricing models. 73-78
  
• Kaveh Aasaraai, Andreas Moshovos:
  Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. 79-85
  

Partial Runtime Reconfiguration

• Marco D. Santambrogio, Massimo Morandi, Marco Novati, Donatella Sciuto:
  A runtime relocation based workflow for self dynamic reconfigurable systems design. 86-91
  
• Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
  An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. 92-98
  
• Jonathan Heiner, Benjamin Sellers, Michael J. Wirthlin, Jeff Kalb:
  FPGA partial reconfiguration via configuration scrubbing. 99-104
  

Synthesis, Low Power

• Jason Helge Anderson, Qiang Wang:
  Improving logic density through synthesis-inspired architecture. 105-111
  
• Safeen Huda, Muntasir Mallick, Jason Helge Anderson:
  Clock gating architectures for FPGA power reduction. 112-118
  
• Heiner Giefers, Marco Platzner:
  Program-driven fine-grained power management for the reconfigurable mesh. 119-125
  

GPU, CPU, FPGA and Image Processing

• Shuichi Asano, Tsutomu Maruyama, Yoshiki Yamaguchi:
  Performance comparison of FPGA, GPU and CPU in image processing. 126-131
  
• Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich:
  Self-organizing multi-cue fusion for FPGA-based embedded imaging. 132-137
  
• Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele:
  Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. 138-145
  

Placement and Routing

• Scott Y. L. Chin, Steven J. E. Wilton:
  An analytical model relating FPGA architecture and place and route runtime. 146-153
  
• David Leong, Guy G. Lemieux:
  Replace: An incremental placement algorithm for field programmable gate arrays. 154-161
  
• Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
  Optimal runtime reconfiguration strategies for systolic arrays. 162-167
  

Applications #1

• Daniel L. Ly, Paul Chow:
  A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. 168-173
  
• Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis:
  Comparing fine-grained performance on the Ambric MPPA against an FPGA. 174-179
  
• Caglar Kalaycioglu, Onur Can Ulusel, Ilker Hamzaoglu:
  Low power techniques for Motion Estimation hardware. 180-185
  

Fault Toleance and Reliability

• Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye:
  Coarse-grained dynamically reconfigurable architecture with flexible reliability. 186-192
  
• Konstantinos Kyriakoulakos, Dionisios N. Pnevmatikatos:
  A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. 193-198
  
• Adam Jacobs, Alan D. George, Grzegorz Cieslewski:
  Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space. 199-204
  

FPGA Architectures

• Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
  Modeling post-techmapping and post-clustering FPGA circuit depth. 205-211
  
• Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
  Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. 212-217
  

Surveys, Trends

• Andreas Ehliar, Dake Liu:
  An ASIC perspective on FPGA optimizations. 218-223
  
• Iouliia Skliarova, Valery Sklyarov:
  Recursion in reconfigurable computing: A survey of implementation approaches. 224-229
  
• Roberto Selow, Heitor S. Lopes, Carlos R. Erig Lima:
  A comparison of FPGA and FPAA technologies for a signal processing application. 230-235
  

Arithmetic

• Dong Wang, Milos D. Ercegovac, Nanning Zheng:
  A radix-8 complex divider for FPGA implementation. 236-241
  
• Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
  Exploiting fast carry-chains of FPGAs for designing compressor trees. 242-249
  
• Florent de Dinechin, Bogdan Pasca:
  Large multipliers with fewer DSP blocks. 250-255
  

Interconnect (classical)

• Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
  Area estimation and optimisation of FPGA routing fabrics. 256-261
  
• Bita Nezamfar, Mark Horowitz:
  In field, energy-performance tunable FPGA architectures. 262-267
  
• Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck:
  Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. 268-275
  

Image Processing Applications

• Joannis Sotiropoulos, Ioannis Papaefstathiou:
  A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems. 276-281
  
• Dimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos:
  Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths. 282-287
  
• Kentaro Kokufuta, Tsutomu Maruyama:
  Real-time processing of local contrast enhancement on FPGA. 288-293
  

Methodologies

• Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
  Enhancements to FPGA design methodology using streaming. 294-301
  
• Josef Angermeier, Abdulazim Amouri, Jürgen Teich:
  General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. 302-307
  
• Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides:
  Optimising designs by combining model-based and pattern-based transformations. 308-313
  

Interconnect (NoC)

• Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli:
  sFPGA2 - A scalable GALS FPGA architecture and design methodology. 314-319
  
• Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker:
  Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. 320-325
  
• Slavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda:
  A new deadlock-free fault-tolerant routing algorithm for NoC interconnections. 326-331
  

Application Acceleration #1

• Toyokazu Takagi, Tsutomu Maruyama:
  Accelerating HMMER search using FPGA. 332-337
  
• Tobias Schumacher, Christian Plessl, Marco Platzner:
  An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure. 338-344
  
• Matt Chiu, Martin C. Herbordt:
  Efficient particle-pair filtering for acceleration of molecular dynamics simulation. 345-352
  

Applications #2

• Florent Camarda, Jean-Christophe Prévotet, Fabienne Nouvel:
  Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting. 353-358
  
• Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
  Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. 359-366
  
• Sang Kyun Kim, Lawrence C. McAfee, Peter Leonard McMahon, Kunle Olukotun:
  A highly scalable Restricted Boltzmann Machine FPGA implementation. 367-372
  

Cryptography, Networking

• Tomasz Kryjak, Marek Gorgon:
  Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA. 373-378
  
• Carles Nicolau, Dolors Sala, Enrique Cantó:
  Clock duplicity for high-precision timestamping in Gigabit Ethernet. 379-384
  
• Rajesh Velegalati, Jens-Peter Kaps:
  DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs. 385-390
  

Watermarking, Chip ID, IP Protection

• Hiren Patel, Yong C. Kim, J. Todd McDonald, LaVern A. Starman:
  Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis. 391-396
  
• Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf:
  Towards a unique FPGA-based identification circuit using process variations. 397-402
  
• Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz:
  IP protection in Partially Reconfigurable FPGAs. 403-409
  

Application Acceleration #2

• Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu:
  FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. 410-416
  
• Wim Vanderbauwhede, Leif Azzopardi, Mahmoud Moadeli:
  FPGA-accelerated Information Retrieval: High-efficiency document filtering. 417-422
  

Acceleration of Video Applications

• Trevor Spiteri, George Vafiadis, Jose Luis Nunez-Yanez:
  A toolset for the analysis and optimization of motion estimation algorithms and processors. 423-428
  
• Enrique Cantó, Mariano Fons, Mariano López-Farcía, Rafael Ramos-Lara:
  Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3. 429-434
  

Poster Session 1

• Jason Agron, David L. Andrews:
  Building heterogeneous reconfigurable systems using threads. 435-438
  
• Angel Quiros-Olozabal, Juan Manuel Barrientos-Villar, Ma de los Angeles Cifredo Chacon:
  Reconfiguration-based time-to-digital converter for Virtex FPGAs. 439-443
  
• Mario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard, Pierre Lacroix, Jean-Yves Fourniols:
  An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis. 444-447
  
• Gustavo Sutter, Jean-Pierre Deschamps:
  High speed fixed point dividers for FPGAs. 448-452
  
• Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas, Ioannis Papaefstathiou:
  A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms. 453-456
  
• Ricardo Menotti, João M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques:
  Automatic generation of FPGA hardware accelerators using a domain specific language. 457-461
  
• Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera:
  A dynamically reconfigurable parallel pixel processing system. 462-466
  
• Jano Gebelein, Heiko Engel, Udo Kebschull:
  An approach to system-wide fault tolerance for FPGAs. 467-471
  
• Adam Arnesen, Nathan Rollins, Michael J. Wirthlin:
  A multi-layered XML schema and design tool for reusing and integrating FPGA IP. 472-475
  
• Benjamin Sellers, Jonathan Heiner, Michael J. Wirthlin, Jeff Kalb:
  Bitstream compression through frame removal and partial reconfiguration. 476-480
  
• Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
  Operation scheduling for FPGA-based reconfigurable computers. 481-484
  
• Alejandro Nieto, Victor M. Brea, David López Vilariño:
  FPGA-accelerated retinal vessel-tree extraction. 485-488
  
• David W. Thöni, Alfred Strey:
  Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm. 489-492
  

Poster Session 2

• R. Porter, S. J. Stone, Y. C. Kim, J. T. McDonald, L. A. Starman:
  Dynamic Polymorphic Reconfiguration for anti-tamper circuits. 493-497
  
• Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch:
  Run-time Partial Reconfiguration speed investigation and architectural design space exploration. 498-502
  
• Romuald Girardey, Michael Hübner, Jürgen Becker:
  Dynamic reconfigurable mixed-signal architecture for safety critical applications. 503-506
  
• Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
  Using 3D integration technology to realize multi-context FPGAs. 507-510
  
• Hironobu Morita, Minoru Watanabe:
  Mems optically reconfigurable gate array. 511-515
  
• Cem Savas Bassoy, Henning Manteuffel, Friedrich Mayer-Lindenberg:
  Sharf: An FPGA-based customizable processor architecture. 516-520
  
• Jiri Halak:
  Multigigabit network traffic processing. 521-524
  
• Rohit Kumar, Ann Gordon-Ross:
  Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs. 525-529
  
• Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano:
  Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. 530-533
  
• Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala:
  A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. 534-538
  

Poster Session 3

• Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan:
  Rapid design exploration framework for application-aware customization of soft core processors. 539-542
  
• Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
  A novel states recovery technique for the TMR softcore processor. 543-546
  
• Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton:
  Performance metrics for hybrid multi-tasking systems. 547-550
  
• Enno Lübbers, Marco Platzner:
  Cooperative multithreading in dynamically reconfigurable systems. 551-554
  
• Venelin Angelov, Volker Lindenstruth:
  The educational processor Sweet-16. 555-559
  
• An Braeken, Serge Kubera, Frederik Trouillez, Abdellah Touhafi, Nele Mentens, Jo Vliegen:
  Secure FPGA technologies and techniques. 560-563
  
• Mariette Awad:
  FPGA supercomputing platforms: A survey. 564-568
  
• Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Perez, Armando Astarloa:
  A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs. 569-573
  
• Mohammad Hosseinabady, José L. Núñez-Yáñez:
  Run-time resource management in fault-tolerant network on reconfigurable chips. 574-577
  
• Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
  Hot-Swapping architecture extension for mitigation of permanent functional unit faults. 578-581
  
• Rafael Ramos-Lara, Mariano Lopez Garcia, Enrique F. Canto Navarro, Luis Puente-Rodriguez:
  SVM speaker verification system based on a low-cost FPGA. 582-586
  
• Chang Choo, Bhavya Bambhania, Woon Seob So, In Ki Hwang, Do Young Kim:
  An FPGA-based embedded wideband audio codec system. 587-590
  

Poster Session 4

• Ikbel Belaid, Fabrice Muller, Benjemaa Maher:
  Off-line placement of hardware tasks on FPGA. 591-595
  
• Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier, Abelardo López-Lagunas:
  Proteus: An architectural synthesis tool based on the stream programming paradigm. 596-599
  
• Yosi Ben-Asher, Nadav Rotem:
  Binary Synthesis with multiple memory banks targeting array references. 600-603
  
• Thomas B. Preußer, Rainer G. Spallek:
  Mapping basic prefix computations to fast carry-chain structures. 604-608
  
• Roberto Gutierrez, Javier Valls, Asuncion Perez-Pascual:
  FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. 609-612
  
• N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung:
  Compensating for variability in FPGAs by re-mapping and re-placement. 613-616
  
• Nick Gasson, Neil C. Audsley:
  Synthesis of the SR programming language for complex FPGAs. 617-621
  
• Maurizio Tranchero, Leonardo Maria Reyneri:
  Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs. 622-625
  
• Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers:
  Using C-to-gates to program streaming image processing kernels efficiently on FPGAs. 626-630
  
• Heiner Litz, Holger Fröning, Maximilian Thürmer, Ulrich Brüning:
  An FPGA based verification platform for HyperTransport 3.x. 631-634
  
• Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
  A virus scanning engine using a parallel finite-input memory machine and MPUs. 635-639
  
• Martin Zádník, Marco Canini, Andrew W. Moore, David J. Miller, Wei Li:
  Tracking elephant flows in internet backbone traffic with an FPGA-based cache. 640-644
  

Poster Session 5

• Maroun Ojail, Raphaël David, Stéphane Chevobbe, Didier Demigny:
  A reconfigurable FIR/FFT unit for wireless telecommunication systems. 645-648
  
• Lubos Gaspar, Milos Drutarovský, Viktor Fischer, Nathalie Bochard:
  Efficient AES S-boxes implementation for non-volatile FPGAs. 649-653
  
• Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
  Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs. 654-657
  
• Panasayya Yalla, Jens-Peter Kaps:
  Compact FPGA implementation of Camellia. 658-661
  
• Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Feng-Hsiung Hsu:
  FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture. 662-665
  
• Jose Manuel Romero-Ximil, Arturo Diaz-Perez:
  An FPGA design for evaluating score function in protein energy calculation. 666-669
  
• Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire, Qingxiang Wu:
  Emulating Spiking Neural Networks for edge detection on FPGA hardware. 670-673
  
• Nikolaos Alachiotis, Alexandros Stamatakis, Euripides Sotiriades, Apostolos Dollas:
  A reconfigurable architecture for the Phylogenetic Likelihood Function. 674-678
  
• Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano:
  Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. 679-682
  
• Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas:
  A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM). 683-686
  
• Guillermo Botella Juan, Antonio García Ríos, Uwe Meyer-Bäse, Manuel Rodríguez, María C. Molina, Luís Parrilla Roure:
  Enhanced gradient-based motion vector coprocessor. 687-690
  
• Saya Hinaga, Yoshiki Yamaguchi, Tetsuhiko Yao, Tohru Kawabe:
  Dynamic reconfiguration system for real-time video processing. 691-694
  
• Hans-Jörg Pfleiderer, Stefan Lachowicz:
  Numerically controlled oscillators using linear approximation. 695-698
  
• Vladimir Rozic, Ingrid Verbauwhede:
  Random numbers generation: Investigation of narrowtransitions suppression on FPGA. 699-702
  
• Abhranil Maiti, Patrick Schaumont:
  Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators. 703-707
  
• Fabio Garzia, Waqar Hussain, Jari Nurmi:
  CREMA: A coarse-grain reconfigurable array with mapping adaptiveness. 708-712
  

PhD Forum Presentations

• Zain-ul-Abdin:
  High-level programming of coarse-grained reconfigurable architectures. 713-714
  
• Carlos González, Daniel Mozos, Javier Resano:
  FPGA support for satellite computations of hyper spectral images. 715-716
  
• Scott Y. L. Chin, Steven J. E. Wilton:
  Improving the memory footprint and runtime scalability of FPGA CAD algorithms. 717-718
  
• J. I. Villar, J. Juan, Manuel J. Bellido:
  Efficient techniques and methodologies for embedded system design usign free hardware and open standards. 719-720
  
• Petr Mikusek:
  Multi-terminal BDD synthesis and applications. 721-722
  
• Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante:
  Soft errors in Flash-based FPGAs: Analysis methodologies and first results. 723-724
  
• Lars Bauer, Muhammad Shafique, Jörg Henkel:
  RISPP: A run-time adaptive reconfigurable embedded processor. 725-726
  

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