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ORCIDBrent E. Nelson
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- affiliation: Brigham Young University, Provo, Utah, USA
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2010 – 2019
- 2019
[c61]Brent E. Nelson
:
Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape. ARC 2019: 353-367- [c60]Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin:
Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules. FCCM 2019: 9-16 - [c59]Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin:
Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs. FPGA 2019: 306-307 - 2017
- [c58]Thomas Townsend, Brent E. Nelson:
Vivado design interface: An export/import capability for Vivado FPGA designs. FPL 2017: 1-7 - 2016
- [c57]Luke Newmeyer, Doran Wilde, Brent E. Nelson, Michael J. Wirthlin:
Efficient processing of phased array radar in sense and avoid application using heterogeneous computing. FPL 2016: 1-8 - [c56]Thomas Townsend, Brent E. Nelson, Michael J. Wirthlin:
An XDL alternative for interfacing RapidSmith and Vivado. FPL 2016: 1 - [c55]Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
Packing a modern Xilinx FPGA using RapidSmith. ReConFig 2016: 1-6 - 2015
- [c54]Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. FPGA 2015: 66-69 - 2014
- [c53]Brad White, Brent E. Nelson:
Tincr - A custom CAD tool framework for Vivado. ReConFig 2014: 1-6 - 2013
- [c52]Travis Haroldsen, Brent E. Nelson, Brad White:
Rapid FPGA design prototyping through preservation of system logic: A case study. FPL 2013: 1-7 - [c51]Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Impact of hard macro size on FPGA clock rate and place/route time. FPL 2013: 1-6 - [c50]Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Improving clock-rate of hard-macro designs. FPT 2013: 246-253 - 2011
- [c49]Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. FCCM 2011: 117-124 - [c48]Subhrashankha Ghosh, Brent E. Nelson:
XDL-Based Module Generators for Rapid FPGA Design Implementation. FPL 2011: 64-69 - [c47]Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. FPL 2011: 349-355 - 2010
- [j16]Dah-Jye Lee, Paul C. Merrell, Zhaoyi Wei, Brent E. Nelson:
Two-frame structure from motion using optical flow probability distributions for unmanned air vehicle obstacle avoidance. Mach. Vis. Appl. 21(3): 229-240 (2010) - [j15]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald:
Hardware-Friendly Vision Algorithms for Embedded Obstacle Detection Applications. IEEE Trans. Circuits Syst. Video Technol. 20(11): 1577-1589 (2010) - [j14]John Bodily, Brent E. Nelson, Zhaoyi Wei, Dah-Jye Lee, Jeff Chase:
A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs. ACM Trans. Reconfigurable Technol. Syst. 3(2): 6:1-6:22 (2010) - [c46]Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin:
Using Hard Macros to Reduce FPGA Compilation Time. FPL 2010: 438-441 - [c45]Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent E. Nelson, Michael Rice, Michael J. Wirthlin:
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis. FPL 2010: 538-543 - [c44]Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
Rapid prototyping tools for FPGA designs: RapidSmith. FPT 2010: 353-356
2000 – 2009
- 2009
- [j13]Dah-Jye Lee, Paul C. Merrell, Brent E. Nelson, Zhaoyi Wei:
Multi-frame structure from motion using optical flow probability distributions. Neurocomputing 72(4-6): 1032-1041 (2009) - [c43]Brent E. Nelson:
FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda. ARC 2009: 1 - [c42]Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis:
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). FCCM 2009: 141-148 - [c41]Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis:
Comparing fine-grained performance on the Ambric MPPA against an FPGA. FPL 2009: 174-179 - [e1]Martin Danek, Jiri Kadlec, Brent E. Nelson:
19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic. IEEE 2009, ISBN 978-1-4244-3892-1 [contents] - 2008
- [j12]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald, Barrett Edwards:
FPGA-Based Embedded Motion Estimation Sensor. Int. J. Reconfigurable Comput. 2008: 636145:1-636145:8 (2008) - [j11]Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin:
Design, Debug, Deploy: The Creation of Configurable Computing Applications. J. Signal Process. Syst. 53(1-2): 187-196 (2008) - [c40]Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn A. Bohner:
Design Productivity for Configurable Computing. ERSA 2008: 57-66 - [c39]Jeff Chase, Brent E. Nelson, John Bodily, Zhaoyi Wei, Dah-Jye Lee:
Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study. FCCM 2008: 173-182 - [c38]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald:
Real-time accurate optical flow-based motion sensor. ICPR 2008: 1-4 - [c37]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, Kirt D. Lillywhite:
Accurate Optical Flow Sensor for Obstacle Avoidance. ISVC (1) 2008: 240-247 - 2007
- [j10]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson:
FPGA-based Real-time Optical Flow Algorithm Design and Implementation. J. Multim. 2(5): 38-45 (2007) - [c36]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson:
A Hardware-Friendly Adaptive Tensor Based Optical Flow Algorithm. ISVC (2) 2007: 43-51 - [c35]Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, Michael Martineau:
A Fast and Accurate Tensor-based Optical Flow Algorithm Implemented in FPGA. WACV 2007: 18 - 2006
- [c34]Brent E. Nelson:
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines. ASAP 2006: 5-14 - 2005
- [c33]Bryan Catanzaro, Brent E. Nelson:
Higher Radix Floating-Point Representations for FPGA-Based Arithmetic. FCCM 2005: 161-170 - [c32]Bryan Catanzaro, Brent E. Nelson:
Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). FPGA 2005: 279 - [c31]Clint Hilton, Brent E. Nelson:
A Flexible Circuit-Switched NOC for FPGA-Based Systems. FPL 2005: 191-196 - 2004
- [j9]Brad L. Hutchings, Brent E. Nelson:
GigaOp DSP on FPGA. J. VLSI Signal Process. 36(1): 41-55 (2004) - [c30]Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner:
JHDLBits: The Merging of Two Worlds. FPL 2004: 414-423 - [c29]Joseph M. Palmer, Brent E. Nelson:
A Parallel FFT Architecture for FPGAs. FPL 2004: 948-953 - 2003
- [c28]Xiaojun Wang, Brent E. Nelson:
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. FCCM 2003: 195- - [c27]Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings:
Reconfigurable Computing Application Frameworks. FCCM 2003: 251- - 2002
- [c26]Eric Roesler, Brent E. Nelson:
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. FPL 2002: 637-646 - [c25]Eric Roesler, Brent E. Nelson:
Debug methods for hybrid CPU/FPGA systems. FPT 2002: 243-250 - 2001
- [j8]Brad L. Hutchings, Brent E. Nelson:
Unifying simulation and execution in a design environment for FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 201-205 (2001) - [c24]Paul S. Graham, Brent E. Nelson, Brad L. Hutchings:
Instrumenting Bitstreams for Debugging FPGA Circuits. FCCM 2001: 41-50 - [c23]Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings:
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. FPL 2001: 483-492 - [c22]Brad L. Hutchings, Brent E. Nelson:
Gigaop DSP on FPGA. ICASSP 2001: 885-888 - 2000
- [j7]Brad L. Hutchings, Brent E. Nelson, Michael J. Wirthlin:
Designing and Debugging Custom Computing Applications. IEEE Des. Test Comput. 17(1): 20-28 (2000) - [c21]Brad L. Hutchings, Brent E. Nelson:
Using general-purpose programming languages for FPGA design. DAC 2000: 561-566 - [c20]Stephen M. Scalera, Mark Falco, Brent E. Nelson:
A Reconfigurable Computing Architecture for Microsensors. FCCM 2000: 59-67 - [c19]Paul S. Graham, Brad L. Hutchings, Brent E. Nelson:
Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings. FCCM 2000: 305-306
1990 – 1999
- 1999
- [j6]Gregory C. Ahlquist, Michael Rice, Brent E. Nelson:
Error control coding in software radios: an FPGA approach. IEEE Wirel. Commun. 6(4): 35-39 (1999) - [c18]Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting:
A CAD Suite for High-Performance FPGA Design. FCCM 1999: 12-24 - [c17]Paul S. Graham, Brent E. Nelson:
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. FPL 1999: 1-10 - [c16]Gregory C. Ahlquist, Brent E. Nelson, Michael Rice:
Optimal Finite Field Multipliers for FPGAs. FPL 1999: 51-60 - 1998
- [c15]Paul S. Graham, Brent E. Nelson:
Frequency-Domain Sonar Processing in FPGAs and DSPs. FCCM 1998: 306-307 - [c14]Paul S. Graham, Brent E. Nelson:
FPGA-Based Sonar Processing. FPGA 1998: 201-208 - 1996
- [j5]Knuth Stener Grimsrud, James K. Archibald, Richard L. Frost, Brent E. Nelson:
Locality as a Visualization Tool. IEEE Trans. Computers 45(11): 1319-1326 (1996) - [c13]Paul S. Graham, Brent E. Nelson:
Genetic algorithms in software and in hardware-a performance analysis of workstation and custom computing machine implementations. FCCM 1996: 216-225 - [c12]J. Kelly Flanagan, Brent E. Nelson, James K. Archibald, Gregory D. Thompson:
The Inaccuracy of Trace-Driven Simulation Using Incomplete Mulitprogramming Trace Data. MASCOTS 1996: 37-43 - [c11]Brent E. Nelson, Gregory D. Thompson, J. Kelly Flanagan:
Transaction Processing Workloads - A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Studies. MASCOTS 1996: 152-156 - 1995
- [c10]Paul S. Graham, Brent E. Nelson:
A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2. FPL 1995: 352-361 - 1994
- [c9]Knuth Stener Grimsrud, James K. Archibald, Richard L. Frost, Brent E. Nelson:
On the Accuracy of Memory Reference Models. Computer Performance Evaluation 1994: 369-388 - 1993
- [j4]Knuth Stener Grimsrud, James K. Archibald, M. Ripley, J. Kelly Flanagan, Brent E. Nelson:
BACH: a hardware monitor for tracing microprocessor-based systems. Microprocess. Microsystems 17(8): 443-459 (1993) - [j3]Robert B. Smith, James K. Archibald, Brent E. Nelson:
Evaluating Performance of Prefetching Second Level Caches. SIGMETRICS Perform. Evaluation Rev. 20(4): 31-42 (1993) - [j2]Knuth Stener Grimsrud, James K. Archibald, Brent E. Nelson:
Multiple Prefetch Adaptive Disk Caching. IEEE Trans. Knowl. Data Eng. 5(1): 88-103 (1993) - [c8]J. Kelly Flanagan, Brent E. Nelson, James K. Archibald, Knuth Stener Grimsrud:
Incomplete Trace Data and Trace Driven Simulation. MASCOTS 1993: 203-209 - 1991
- [c7]Brent E. Nelson, James K. Archibald, J. Kelly Flanagan:
Performance analysis of inclusion effects in multi-level multiprocessor caches. SPDP 1991: 513-516
1980 – 1989
- 1989
- [c6]J. Kelly Flanagan, Darryl Morrell, Richard L. Frost, Christopher J. Read, Brent E. Nelson:
Vector quantization codebook generation using simulated annealing. ICASSP 1989: 1759-1762 - 1988
- [c5]J. Kelly Flanagan, Brent E. Nelson:
Processor design using path programmable logic. ICCD 1988: 196-199 - 1987
- [c4]Tao Li, Brent E. Nelson, J. Kelly Flanagan, Christopher J. Read:
A multiprogrammed parallel architecture for digital signal processing. ICASSP 1987: 1390-1393 - 1986
- [c3]Brent E. Nelson, Christopher J. Read:
A bit-serial VLSI vector quantizer. ICASSP 1986: 2211-2214 - 1984
- [j1]Elliott I. Organick, Tony M. Carter, Mike P. Maloney, Alan L. Davis, Alan B. Hayes, Dan Klass, Gary Lindstrom, Brent E. Nelson, Kent F. Smith:
Transforming an Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Environment: A first Experiment. IEEE Softw. 1(1): 31-49 (1984) - [c2]Tony M. Carter, Alan L. Davis, Alan B. Hayes, Gary Lindstrom, Dan Klass, Mike P. Maloney, Brent E. Nelson, Elliott I. Organick, Kent F. Smith:
Transforming an Ada Program Unit to Silicon and Testing It in an Ada Environment. COMPCON 1984: 448-455 - [c1]Lee A. Hollaar, Brent E. Nelson, Tony M. Carter, Raymond A. Lorie:
The structure and operation of a relational database system in a cell-oriented integrated circuit design system. DAC 1984: 117-125
Coauthor Index
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