Technologies and Trends

• 
  Steve Ferrera, Nicholas P. Carter: Reconfigurable Circuits Using Hybrid Hall Effect Devices. 1-10
• 
  Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald: Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. 11-20

Communications Applications

• 
  Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu: Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. 21-30
• 
  Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre: Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S. 31-40

High Level Design Tools 1

• 
  Sumit Mohanty, Viktor K. Prasanna: An Algorithm Designer's Workbench for Platform FPGA's. 41-50
• 
  Ludovico de Souza, Philip J. Ryan, Jason Crawford, Kevin Wong, Gregory B. Zyner, Tom McDermott: Prototyping for the Concurrent Development. 51-60

Reconfigurable Architectures

• 
  Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins: ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. 61-70
• 
  Eryk Laskowski, Marek Tudruj: Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches. 71-80
• 
  Georgi Kuzmanov, Stamatis Vassiliadis: Arbitrating Instructions in an pmu-Coded CCM. 81-90

Cryptographic Applications 1

• 
  Thomas J. Wollinger, Christof Paar: How Secure Are FPGAs in Cryptographic Applications? 91-100
• 
  Jean-Luc Beuchat: FPGA Implementations of the RC6 Block Cipher. 101-110
• 
  Máire McLoone, John V. McCanny: Very High Speed 17 Gbps SHACAL Encryption Architecture. 111-120

Place and Route Tools

• 
  Katherine Compton, Scott Hauck: Track Placement: Orchestrating Routing Structures to Maximize Routability. 121-130
• 
  Sean T. McCulloch, James P. Cohoon: Quark Routing. 131-140
• 
  Jorge Barreiros, Ernesto Costa: Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms. 141-150

Multi-context FPGAs

• 
  Rolf Enzler, Christian Plessl, Marco Platzner: Virtualizing Hardware with Multi-context Reconfigurable Arrays. 151-160
• 
  Hideharu Amano, Akiya Jouraku, Kenichiro Anjo: A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. 161-170
• 
  Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo: Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. 171-180

Cryptographic Applications 2

• 
  Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat: Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. 181-193
• 
  Ivan Gonzalez, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez: Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. 194-203
• 
  Allen Michalski, Kris Gaj, Tarek A. El-Ghazawi: An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. 204-219

Low-Power Issues 1

• 
  Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo: Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. 220-229
• 
  Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal: Low Power Coarse-Grained Reconfigurable Instruction Set Processor. 230-239
• 
  Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick: Encoded-Low Swing Technique for Ultra Low Power Interconnect. 240-251

Run-Time Configurations

• 
  Gareth Lee, George Milne: Building Run-Time Reconfigurable Systems from Tiles. 252-261
• 
  Irwin Kennedy: Exploiting Redundancy to Speedup Reconfiguration of an FPGA. 262-271
• 
  Klaus Danne, Christophe Bobda, Heiko Kalte: Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration. 272-281

Cryptographic Applications 3

• 
  François Charot, Eslam Yahya, Charles Wagner: Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. 282-291
• 
  Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo: An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. 292-302
• 
  Nazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez: Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core. 303-312

Compilation Tools

• 
  K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. 313-323
• 
  Henry Styles, Wayne Luk: Branch Optimisation Techniques for Hardware Compilation. 324-333
• 
  Jirong Liao, Weng-Fai Wong, Tulika Mitra: A Model for Hardware Realization of Kernel Loops. 334-344

Asynchronous Techniques

• 
  John Teifel, Rajit Manohar: Programmable Asynchronous Pipeline Arrays. 345-354
• 
  Andrew Royal, Peter Y. K. Cheung: Globally Asynchronous Locally Synchronous FPGA Architectures. 355-364

Biology-Related Applications

• 
  Tom Van Court, Martin C. Herbordt, Richard J. Barton: Case Study of a Functional Genomics Application. 365-374
• 
  Chi Wai Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai Leong: A Smith-Waterman Systolic Cell. 375-384

Codesign

• 
  Eric Keller, Gordon J. Brebner, Philip James-Roxby: Software Decelerators. 385-395
• 
  Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. 396-405

Reconfigurable Fabrics

• 
  Herman Schmit: Extra-dimensional Island-Style FPGAs. 406-415
• 
  Tony Stansfield: Using Multiplexers for Control and Data in D-Fabrix. 416-425
• 
  Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit: Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. 426-436

Image Processing Applications

• 
  Toshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama: A Real-Time Visualization System for PIV. 437-447
• 
  Yosuke Miyajima, Tsutomu Maruyama: A Real-Time Stereo Vision System with FPGA. 448-457
• 
  Jose Antonio Boluda, Fernando Pardo: Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System. 458-467

SAT Techniques

• 
  Iouliia Skliarova, António de Brito Ferrari: Reconfigurable Hardware SAT Solvers: A Survey of Systems. 468-477
• 
  Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich: Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. 478-487
• 
  Roland H. C. Yap, Stella Z. Q. Wang, Martin Henz: Hardware Implementations of Real-Time Reconfigurable WSAT Variants. 488-496

Application-Specific Architectures

• 
  Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría: Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. 497-506
• 
  Seonil Choi, Viktor K. Prasanna: Time and Energy Efficient Matrix Factorization Using FPGAs. 507-519
• 
  John Oliver, Venkatesh Akella: Improving DSP Performance with a Small Amount of Field Programmable Logic. 520-532

DSP Applications

• 
  Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco Ballester, Francisco Mora Campos: Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. 533-542
• 
  Stavros Paschalakis, Peter Lee, Miroslaw Bober: An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors. 543-552
• 
  Abdsamad Benkrid, Khaled Benkrid, Danny Crookes: Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. 553-564

Dynamic Reconfiguration

• 
  Brandon Blodget, Philip James-Roxby, Eric Keller, Scott McMillan, Prasanna Sundararajan: A Self-reconfiguring Platform. 565-574
• 
  Christoph Steiger, Herbert Walder, Marco Platzner: Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices. 575-584
• 
  Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor: Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. 585-594

SoC Architectures

• 
  Théodore Marescaux, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins: Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. 595-605
• 
  N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. 606-615

Emulation

• 
  Matteo Sonza Reorda, Massimo Violante: Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. 616-626
• 
  M. Çakir, Eike Grimpe, Wolfgang Nebel: HW-Driven Emulation with Automatic Interface Generation. 627-637

Cache Design

• 
  Shih-Lien Lu, Konrad Lai: Implementation of HW$im - A Real-Time Configurable Cache Simulator. 638-647
• 
  Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike H. MacGregor: The Bank Nth Chance Replacement Policy for FPGA-Based CAMs. 648-660

Arithmetic 1

• 
  Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo: Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. 661-669
• 
  Chang Hoon Kim, Soonhak Kwon, Jong Jin Kim, Chun Pyo Hong: A New Arithmetic Unit in GF(2^m) for Reconfigurable Hardware Implementation. 670-680

Biologically Inspired Designs

• 
  Yann Thoma, Eduardo Sanchez, Juan-Manuel Moreno Aróstegui, Gianluca Tempesti: A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit. 681-690
• 
  Leonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez, Christian A. Morillas, Samuel F. Romero: An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time. 691-700

Low-Power Issues 2

• 
  François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques Quisquater: Power Analysis of FPGAs: How Practical is the Attack? 701-711
• 
  Maurizio Martina, Andrea Molino, Federico Quaglio, Fabrizio Vacca: A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications. 712-721

SoC Designs

• 
  Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny: A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. 722-732
• 
  Martin Delvai, Ulrike Eisenmann, Wilfried Elmenreich: A Generic Architecture for Integrated Smart Transducers. 733-744
• 
  Nuno Roma, Tiago Dias, Leonel Sousa: Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs. 745-754

Cellular Applications

• 
  Tomoyoshi Kobori, Tsutomu Maruyama: A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA. 755-765
• 
  Yasunori Osana, Tomonori Fukushima, Hideharu Amano: Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. 766-775
• 
  Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia: On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. 776-785

Arithmetic 2

• 
  Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici: Fast Modular Division for Application in ECC on Reconfigurable Logic. 786-795
• 
  Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: Non-uniform Segmentation for Hardware Function Evaluation. 796-807
• 
  Barry Lee, Neil Burgess: A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA. 808-817

Fault Analysis

• 
  J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto: A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits. 818-827
• 
  Andrzej Krasniewski: Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. 828-838
• 
  Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa: Fault Simulation Using Partially Reconfigurable Hardware. 839-848
• 
  Seyed Ghassem Miremadi, Ali Reza Ejlali: Switch Level Fault Emulation. 849-858

Network Applications

• 
  John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim: An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall. 859-868
• 
  Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj: IPsec-Protected Transport of HDTV over IP. 869-879
• 
  Ioannis Sourdis, Dionisios N. Pnevmatikatos: Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System. 880-889
• 
  T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay: Irregular Reconfigurable CAM Structures for Firewall Applications. 890-899

High Level Design Tools 2

• 
  Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis: Compiling for the Molen Programming Paradigm. 900-910
• 
  Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Laura: Leiden Architecture Research and Exploration Tool. 911-920
• 
  Lilian Bossuet, Guy Gogniat, Jean Luc Philippe: Communication Costs Driven Design Space Exploration for Reconfigurable Architectures. 921-933
• 
  Linda Kaouane, Mohamed Akil, Yves Sorel, Thierry Grandpierre: From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations. 934-943

Technologies and Trends (Posters)

• 
  Stuart Colsell, Reuben Edwards: Adaptive Real-Time Systems and the FPAA. 944-947
• 
  Mark E. Dunham, Michael P. Caffrey, Paul S. Graham: Challenges and Successes in Space Based Reconfigurable Computing. 948-951
• 
  Shigeyuki Takano: Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing. 952-955

Applications (Posters)

• 
  Christopher R. Clark, David E. Schimmel: Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns. 956-959
• 
  Roland Höller: FPGAs for High Accuracy Clock Synchronization over Ethernet Networks. 960-963
• 
  Jiri Novotný, Otto Fucík, David Antos: Project of IPv6 Router with FPGA Hardware Accelerator. 964-967
• 
  David V. Schuehler, Harvey Ku, John W. Lockwood: A TCP/IP Based Multi-device Programming Circuit. 968-971

Tools (Posters)

• 
  Richard H. Turner, Roger Woods: Design Flow for Efficient FPGA Reconfiguration. 972-975
• 
  Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida: High-Level Design Tools for FPGA-Based Combinatorial Accelerators. 976-979
• 
  Daniel Denning, Neil Harold, Malachy Devlin, James Irvine: Using System Generator to Design a Reconfigurable Video Encryption System. 980-983
• 
  Miroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl: MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping. 984-987

FPGA Implementations (Posters)

• 
  J. Marí-Roig, V. Torres, Ma José Canet, A. Perez-Pascual, T. Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat: DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. 988-991
• 
  John A. Nestor: FPGA Implementation of a Maze Routing Accelerator. 992-995
• 
  John Cochran, Deepak Kapur, Darko Stefanovic: Model Checking Reconfigurable Processor Configurations for Safety Properties. 996-999
• 
  Renqiu Huang, Tommy Cheung, Ted Chi-Wah Kok: A Statistical Analysis Tool for FPLD Architectures. 1000-1003

Video and Image Applications (Posters)

• 
  Jörg Velten, Anton Kummert: FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications. 1004-1007
• 
  Cesar Torres-Huitzil, Miguel Arias-Estrada: Configurable Hardware Architecture for Real-Time Window-Based Image Processing. 1008-1011
• 
  Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid: An FPGA-Based Image Connected Component Labeller. 1012-1015
• 
  Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero: FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. 1016-1019

Reconfigurable and Low-Power Systems (Posters)

• 
  Valery Sklyarov, Iouliia Skliarova: Reconfigurable Systems in Education. 1020-1023
• 
  Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto: Data Dependent Circuit Design: A Case Study. 1024-1027
• 
  Maurizio Martina, Andrea Molino, Mario Nicola, Fabrizio Vacca: Design of a Power Conscious, Customizable CDMA Receiver. 1028-1031
• 
  Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. 1032-1035

Design Techniques (Posters)

• 
  Pilar Martínez Ortigosa, O. López, R. Estrada, Inmaculada García, Ester M. Garzón: A VHDL Library to Analyse Fault Tolerant Techniques. 1036-1039
• 
  Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai: Hardware Design with a Scripting Language. 1040-1043
• 
  L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti: Testable Clock Routing Architecture for Field Programmable Gate Arrays. 1044-1047

Neural and Biological Applications (Posters)

• 
  Eva M. Ortigosa, Pilar Martínez Ortigosa, Antonio Cañas, Eduardo Ros, Rodrigo Agís, Julio Ortega: FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition. 1048-1052
• 
  Juan M. Xicotencatl, Miguel Arias-Estrada: FPGA Based High Density Spiking Neural Network Array. 1053-1056
• 
  Jun Jiang, Wayne Luk, Daniel Rueckert: FPGA-Based Computation of Free-Form Deformations. 1057-1061
• 
  Jihan Zhu, Peter Sutton: FPGA Implementations of Neural Networks - A Survey of a Decade of Progress. 1062-1066

Codesign and Embedded Systems (Posters)

• 
  Aurel Netin, Dumitru Roman, Octavian Cret, Kalman Pusztai, Lucia Vacariu: FPGA-Based Hardware/Software CoDesign of an Expert System Shell. 1067-1070
• 
  Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. 1071-1074
• 
  Martin Simka, Viktor Fischer, Milos Drutarovský: Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study. 1075-1078
• 
  Jim Harkin, Michael J. Callaghan, Chris Peters, T. Martin McGinnity, Liam P. Maguire: On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems. 1079-1082

Reconfigurable Systems and Architectures (Posters)

• 
  Christian Schmidt, Andreas Koch: Fast Region Labeling on the Reconfigurable Platform ACE-V. 1083-1086
• 
  Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado: Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications. 1087-1090
• 
  David Rodríguez Lozano, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido: Reconfigurable Hybrid Architecture for Web Applications. 1091-1094

DSP Applications (Posters)

• 
  Antonin Hermanek, Zdenek Pohl, Jiri Kadlec: FPGA Implementation of the Adpaptive Lattice Filter. 1095-1098
• 
  Jonathan Ballagh, James Hwang, H. Ma, Brent Milne, Nabeel Shirazi, Vinay Singh, Jeffrey D. Stroomer: Specifying Control Logic for DSP Applications in FPGA. 1099-1102
• 
  Selene Maya-Rueda, Miguel Arias-Estrada: FPGA Processor for Real-Time Optical Flow Computation. 1103-1106
• 
  María Dolores Valdés, María José Moure, Camilo Quintáns, Enrique Mandado: A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications. 1107-1110

Dynamic Reconfiguration (Posters)

• 
  Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek: Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. 1111-1114
• 
  Dylan Carline, Paul Coulton: A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices. 1115-1118
• 
  Sergej Sawitzki, Rainer G. Spallek: Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. 1119-1122
• 
  Christophe Bobda, Klaus Danne, André Linarth: Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System. 1123-1126

Arithmetic (Posters)

• 
  José Luis Imaña, Juan Manuel Sánchez: A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2^m). 1127-1130
• 
  Fernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather: A Study on the Design of Floating-Point Functions in FPGAs. 1131-1134
• 
  Javier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz: Design and Implementation of RNS-Based Adaptive Filters. 1135-1138
• 
  Sami Khawam, Tughrul Arslan, Fred Westall: Domain-Specific Reconfigurable Array for Distributed Arithmetic. 1139-1144

Design and Implementations 1 (Posters)

• 
  Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino: Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. 1145-1148
• 
  Brendan McAllister, Sakir Sezer, Ciaran Toal: Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. 1149-1152
• 
  Shaomeng Li, Jim Torresen, Oddvar Søråsen: Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware. 1153-1157
• 
  Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes: Propose of a Hardware Implementation for Fingerprint Systems. 1158-1161

Design and Implementations 2 (Posters)

• 
  Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor: APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator. 1162-1165
• 
  Vinu Vijay Kumar, John Lach: Designing, Scheduling, and Allocating Flexible Arithmetic Components. 1166-1169
• 
  Miguel Angel Aguirre Echánove, Jonathan Noel Tombs, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo: UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging. 1170-1173

last updated on Mon May 20 01:59:53 2013 by the dblp team
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