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T. Sansaloni
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2010 – 2019
- 2012
- [j11]Fabian Angarita, Trinidad Sansaloni, María José Canet, Javier Valls
:
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 66(2): 99-104 (2012) - [j10]Fabian Angarita, Trinidad Sansaloni, Asuncion Perez-Pascual, Javier Valls
:
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 68(2): 139-149 (2012) - [c12]Vicente Torres-Carot
, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls
:
Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. ICECS 2012: 408-411
2000 – 2009
- 2009
- [j9]Fabian Angarita, Ma José Canet, Trinidad Sansaloni, Vicenç Almenar
, Javier Valls
:
Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. J. Circuits Syst. Comput. 18(7): 1333-1337 (2009) - [j8]Vicente Torres-Carot
, A. Perez-Pascual, T. Sansaloni, Javier Valls
:
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J. Signal Process. Syst. 56(1): 17-23 (2009) - [j7]A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre
, Javier Valls
:
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. J. Signal Process. Syst. 56(1): 35-40 (2009) - 2008
- [j6]Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls
, Vicenc Almenar-Terre
:
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. J. Signal Process. Syst. 52(1): 35-44 (2008) - [j5]Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls
:
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. J. Signal Process. Syst. 52(2): 181-191 (2008) - 2007
- [j4]Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres-Carot
, Vicenç Almenar
, José F. Toledo, Javier Valls
:
FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. IEEE Trans. Educ. 50(3): 229-235 (2007) - [j3]T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot
, Javier Valls
:
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J. VLSI Signal Process. 47(2): 183-187 (2007) - [c11]A. Perez-Pascual, T. Sansaloni, Vicente Torres
, Vicenç Almenar
, Javier Valls
:
Design of an efficient digital down-converter for a SDR-based DVB-S receiver. ECCTD 2007: 256-259 - [c10]Fabian Angarita Preciado, María José Canet, Trinidad Sansaloni Balaguer, Vicenc Almenar-Terre
, Javier Valls-Coquillat
:
Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN. ICECS 2007: 586-588 - 2006
- [j2]Javier Valls
, Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres
, Vicenç Almenar
:
The use of CORDIC in software defined radios: a tutorial. IEEE Commun. Mag. 44(9): 46-50 (2006) - [c9]Vicente Torres-Carot
, A. Perez-Pascual, T. Sansaloni, Javier Valls
:
Design of high performance timing recovery loops for communication applications. SiPS 2006: 1-4 - 2005
- [c8]Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls
:
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. FPL 2005: 535-538 - 2003
- [j1]T. Sansaloni, Javier Valls
, Keshab K. Parhi
:
Digit-Serial Complex-Number Multipliers on FPGAs. J. VLSI Signal Process. 33(1-2): 105-115 (2003) - [c7]José Marín-Roig, Vicente Torres-Carot, Ma José Canet, Asuncion Perez-Pascual, Trinidad Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat:
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. FPL 2003: 988-991 - 2002
- [c6]A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA-based radix-4 butterflies for HIPERLAN/2. ISCAS (3) 2002: 277-280 - 2001
- [c5]T. Sansaloni, A. Perez-Pascual, Javier Valls:
Distributed arithmetic radix-2 butterflies for FPGA. ICECS 2001: 521-524 - [c4]A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA based on-line complex-number multipliers. ICECS 2001: 1481-1484 - 2000
- [c3]Trinidad Sansaloni, Javier Valls, Keshab K. Parhi
:
FPGA-based digit-serial complex number multiplier-accumulator. ISCAS 2000: 585-588
1990 – 1999
- 1999
- [c2]Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo:
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. ICECS 1999: 241-244 - 1998
- [c1]Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo:
Design and FPGA implementation of digit-serial FIR filters. ICECS 1998: 191-194
Coauthor Index
aka: A. Perez-Pascual
aka: Javier Valls
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