Invited Talk

• 
  David F. Heidel: Single-Event-Upset Trends in Advanced CMOS Technologies.

Adaptive Design and Gate Level Redundancy

• 
  Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Adaptive Design for Performance-Optimized Robustness. 3-11
• 
  Tian Xia, Stephen Wyatt, Rupert Ho: Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration. 12-19
• 
  Kristian Granhaug, Snorre Aunet: Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. 20-28
• 
  Valeriu Beiu, Walid Ibrahim, Y. A. Alkhawwar, Mawahib H. Sulieman: Gate Failures Effectively Shape Multiplexing. 29-40

Delay Test

• 
  Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: Test Generation for Open Defects in CMOS Circuits. 41-49
• 
  Kyriakos Christou, Maria K. Michael, Spyros Tragoudas: Implicit Critical PDF Test Generation with Maximal Test Efficiency. 50-58
• 
  Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz: Selecting High-Quality Delay Tests for Manufacturing Test and Debug. 59-70

Emerging Technologies

• 
  Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi: Testing Reversible 1D Arrays for Molecular QCA. 71-79
• 
  Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park: Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design. 80-88
• 
  Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi: Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. 89-97
• 
  Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim: Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. 98-106
• 
  Reza M. Rad, Mohammad Tehranipoor: A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices. 107-118

Test Compression

• 
  Sverre Wichlund, Frank Berntsen, Einar J. Aas: Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. 119-127
• 
  Hamidreza Hashempour, Fabrizio Lombardi: A Novel Methodology for Functional Test Data Compression. 128-135
• 
  Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito: Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. 136-144
• 
  Geewhun Seok, Il-soo Lee, Tony Ambler, B. F. Womack: An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint. 145-156

Invited Talk

• 
  Krishnendu Chakrabarty: Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.

Defect Tolerance and Error Correction

• 
  Vijay K. Jain, Glenn H. Chapman: Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC. 157-165
• 
  Akhil Garg, Prashant Dubey: Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. 166-174
• 
  Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara: Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. 175-183
• 
  Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang: Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique. 184-196

BIST and Pseudo-Functional Test

• 
  Yuejian Wu, André Ivanov: Low Power SoC Memory BIST. 197-205
• 
  Avijit Dutta, Nur A. Touba: Synthesis of Efficient Linear Test Pattern Generators. 206-214
• 
  Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: An Approach to Minimizing Functional Constraints. 215-226

Reliability Evaluation and Analysis

• 
  Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Adelio Salsano, Fabrizio Lombardi: Reliability Evaluation of Repairable/Reconfigurable FPGAs. 227-235
• 
  Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Reliability Analysis of Self-Repairable MEMS Accelerometer. 236-244
• 
  Sanghoan Chang, Gwan Choi: Timing Failure Analysis of Commercial CPUs Under Operating Stress. 245-253
• 
  André V. Fidalgo, Gustavo R. Alves, José M. Ferreira: Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis. 254-264

Approaches for Soft Errors

• 
  Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. 265-273
• 
  Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara: Low-Cost Hardening of Image Processing Applications Against Soft Errors. 274-279
• 
  Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante: Online hardening of programs against SEUs and SETs. 280-290

Interactive Papers

• 
  Chuen-Song Chen, Jien-Chung Lo, Tian Xia: Equivalent IDDQ Tests for Systems with Regulated Power Supply. 291-299
• 
  Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský: Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. 300-308
• 
  Lei Fang, Michael S. Hsiao: Bilateral Testing of Nano-scale Fault-tolerant Circuits. 309-317
• 
  Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas: A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. 318-326
• 
  Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. 327-335
• 
  Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. 336-344
• 
  Á. Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro: SET Fault Tolerant Combinational Circuits Based on Majority Logic. 345-352
• 
  Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi: An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm. 353-361
• 
  Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li: A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. 362-370
• 
  Marco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano: Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers. 371-379
• 
  Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter: Recovery Mechanisms for Dual Core Architectures. 380-388
• 
  Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli: A Software-Based Error Detection Technique Using Encoded Signatures. 389-400

Diagnosis

• 
  Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. 401-109
• 
  Yukiya Miura, Jiro Kato: Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics. 410-418
• 
  Irith Pomeranz, Sudhakar M. Reddy: Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. 419-427
• 
  Ying-Yen Chen, Jing-Jia Liou: Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method. 428-438

Defect and Fault Tolerance in Sensors and NOCs

• 
  Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapman, Israel Koren, Zahava Koren: On-Line Mapping of In-Field Defects in Image Sensor Arrays. 439-447
• 
  Michelle L. La Haye, Cory Jung, David Chen, Glenn H. Chapman, Jozsef Dudas: Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies. 448-456
• 
  Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande: NoC Interconnect Yield Improvement Using Crosspoint Redundancy. 457-465
• 
  Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu: Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding. 466-476

Test Techniques

• 
  Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi: Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. 477-485
• 
  Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi: Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. 486-494
• 
  Xiaojun Ma, Fabrizio Lombardi: Multi-Site and Multi-Probe Substrate Testing on an ATE. 495-506

Processor Checking and Jitter

• 
  Federico Rota, Shantanu Dutt, Sahithi Krishna: Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. 507-515
• 
  Joonhyuk Yoo, Manoj Franklin: The Filter Checker: An Active Verification Management Approach. 516-524
• 
  Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya: Effect of Process Variation on the Performance of Phase Frequency Detector. 525-534
• 
  Di Mu, Tian Xia, Hao Zheng: Data Dependent Jitter Characterization Based on Fourier Analysis. 534-544

Fault Tolerance Designs

• 
  Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya: A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells. 545-553
• 
  Tadayoshi Horita, Takurou Murata, Itsuo Takanami: A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. 554-562
• 
  Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf: VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. 563-571
• 
  Mehran Mozaffari Kermani, Arash Reyhani-Masoleh: Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard. 572-580

last updated on Sat May 25 04:53:57 2013 by the dblp team
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