default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDRajit Manohar
Person information
- affiliation: Cornell University, Ithaca, NY, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j27]Raghavendra Pradyumna Pothukuchi
, Karthik Sriram, Michal Gerasimiuk, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee:
Distributed Brain-Computer Interfacing With a Networked Multiaccelerator Architecture. IEEE Micro 44(4): 106-115 (2024)- [j26]Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li:
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1683-1689 (2024) - [c92]Esteban Ramos, Robert Soulé, Peter Alvaro, Pietro Bressana, Edmund Chen, Uri Cummings, Rui Li, James Tsai, Rajit Manohar:
Split gRPC: An Isolation Architecture for RPC Software Stacks. APSys 2024: 81-87 - [c91]Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, Maya B. Gokhale:
Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine. DATE 2024: 1-2 - [c90]Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury:
High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. UCNC 2024: 269-285 - 2023
- [j25]Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Ján Veselý, Nick Lindsay, Michael Wu, Lenny Khazan, Raghavendra Pradyumna Pothukuchi, Rajit Manohar, Abhishek Bhattacharjee:
HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro 43(3): 64-72 (2023) - [c89]Prafull Purohit, Johannes Leugering, Rajit Manohar:
An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. ASYNC 2023: 1-10 - [c88]Karthi Srinivasan, Yoram Moses, Rajit Manohar:
Opportunistic Mutual Exclusion. ASYNC 2023: 1-9 - [c87]Rajit Manohar, Yoram Moses:
Timed Signalling Processes. ASYNC 2023: 10-19 - [c86]Xiang Wu, Rajit Manohar:
Verification-Driven Design for Asynchronous VLSI. ASYNC 2023: 78-88 - [c85]Karthik Sriram, Raghavendra Pradyumna Pothukuchi, Michal Gerasimiuk, Muhammed Ugur, Oliver Ye, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee:
SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing. ISCA 2023: 72:1-72:20 - [i9]Karthik Sriram, Raghavendra Pradyumna Pothukuchi, Michal Gerasimiuk, Oliver Ye, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee:
A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing. CoRR abs/2301.03103 (2023) - [i8]Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Michael Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi:
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR abs/2304.04640 (2023) - [i7]Karthi Srinivasan, Yoram Moses, Rajit Manohar:
Opportunistic Mutual Exclusion. CoRR abs/2305.05802 (2023) - [i6]Thomas Jagielski, Rajit Manohar, Jaijeet Roychowdhury:
FPIM: Field-Programmable Ising Machines for Solving SAT. CoRR abs/2306.01569 (2023) - [i5]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023) - 2022
- [j24]Ruslan Dashkin, Rajit Manohar:
General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3452-3465 (2022) - [c84]Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali:
SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity. ASP-DAC 2022: 586-591 - [c83]Rajit Manohar:
Hardware/software Co-design for Neuromorphic Systems. CICC 2022: 1-5 - [c82]Abhishek Bhattacharjee, Rajit Manohar:
HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HCS 2022: 1-37 - [c81]Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher:
A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IPDPS Workshops 2022: 838-847 - 2021
- [j23]Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali:
An Open-Source EDA Flow for Asynchronous Logic. IEEE Des. Test 38(2): 27-37 (2021) - [j22]Ioannis Karageorgos, Karthik Sriram, Ján Veselý, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David A. Borton, Rajit Manohar, Abhishek Bhattacharjee:
Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro 41(3): 87-94 (2021) - [c80]Rui Li, Lincoln Berkley, Yihang Yang, Rajit Manohar:
Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures. ASYNC 2021: 1-8 - [c79]Prafull Purohit, Rajit Manohar:
Hierarchical Token Rings for Address-Event Encoding. ASYNC 2021: 9-16 - [c78]Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé:
Zerializer: towards zero-copy serialization. HotOS 2021: 206-212 - 2020
- [j21]Rajit Manohar:
Exact Timing Analysis for Asynchronous Circuits With Multiple Periods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3134-3138 (2020) - [j20]Ned Bingham, Rajit Manohar:
A Systematic Approach for Arbitration Expressions. IEEE Trans. Circuits Syst. 67-I(12): 4960-4969 (2020) - [c77]Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar:
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. ASYNC 2020: 11-19 - [c76]Samira Ataei, Rajit Manohar:
Shared-Staticizer for Area-Efficient Asynchronous Circuits. ASYNC 2020: 94-101 - [c75]Yihang Yang, Jiayuan He, Rajit Manohar:
Dali: A Gridded Cell Placement Flow. ICCAD 2020: 145:1-145:9 - [c74]Ioannis Karageorgos, Karthik Sriram, Ján Veselý, Michael Wu, Marc Powell, David A. Borton, Rajit Manohar, Abhishek Bhattacharjee:
Hardware-Software Co-Design for Brain-Computer Interfaces. ISCA 2020: 391-404 - [i4]Nathan Manohar, Peter Manohar, Rajit Manohar:
HABIT: Hardware-Assisted Bluetooth-based Infection Tracking. IACR Cryptol. ePrint Arch. 2020: 949 (2020)
2010 – 2019
- 2019
- [j19]Alexander Neckar, Sam Fok, Ben Varkey Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen:
Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model. Proc. IEEE 107(1): 144-164 (2019) - [j18]Ned Bingham, Rajit Manohar:
QDI Constant-Time Counters. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 83-91 (2019) - [j17]Nitish Kumar Srivastava, Rajit Manohar:
Operation-Dependent Frequency Scaling Using Desynchronization. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 799-809 (2019) - [j16]Ned Bingham, Rajit Manohar:
Self-Timed Adaptive Digit-Serial Addition. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2131-2141 (2019) - [c73]Samira Ataei, Rajit Manohar:
AMC: An Asynchronous Memory Compiler. ASYNC 2019: 1-8 - [c72]Rajit Manohar, Yoram Moses:
Asynchronous Signalling Processes. ASYNC 2019: 68-75 - [c71]Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali:
SPRoute: A Scalable Parallel Negotiation-based Global Router. ICCAD 2019: 1-8 - 2018
- [j15]Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis P. Tsividis:
A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption. IEEE J. Solid State Circuits 53(2): 418-430 (2018) - [j14]Wenmian Hua, Rajit Manohar:
Exact Timing Analysis for Asynchronous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 203-216 (2018) - [i3]Saber Moradi, Rajit Manohar:
The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. CoRR abs/1809.06016 (2018) - 2017
- [c70]Rajit Manohar, Yoram Moses:
The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. ASYNC 2017: 102-109 - [c69]Yu Chen, Rajit Manohar, Yannis P. Tsividis:
Design of tunable digital delay cells. CICC 2017: 1-4 - [c68]Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang:
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. FPGA 2017: 195-200 - [c67]Tayyar Rzayev, Saber Moradi, David H. Albonesi, Rajit Manohar:
DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks. IJCNN 2017: 116-124 - [c66]Tayyar Rzayev, David H. Albonesi, François Guimbretière, Rajit Manohar, Jaeyeon Kihm:
Toolbox for exploration of energy-efficient event processors for human-computer interaction. ISPASS 2017: 173-184 - [c65]Asa Dan, Rajit Manohar, Yoram Moses:
On Using Time Without Clocks via Zigzag Causality. PODC 2017: 241-250 - [c64]Saber Moradi, Sunil A. Bhave, Rajit Manohar:
Energy-efficient hybrid CMOS-NEMS LIF neuron circuit in 28 nm CMOS process. SSCI 2017: 1-5 - [i2]Asa Dan, Rajit Manohar, Yoram Moses:
On Using Time Without Clocks via Zigzag Causality. CoRR abs/1705.08627 (2017) - [i1]Saber Moradi, Sunil A. Bhave, Rajit Manohar:
Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28 nm CMOS Process. CoRR abs/1712.07299 (2017) - 2016
- [c63]Sandra J. Jackson, Rajit Manohar:
Gradual Synchronization. ASYNC 2016: 29-36 - 2015
- [j13]Rajit Manohar:
Comparing Stochastic and Deterministic Computing. IEEE Comput. Archit. Lett. 14(2): 119-122 (2015) - [j12]Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha:
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1537-1557 (2015) - [c62]Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar:
Timing Driven Placement for Quasi Delay-Insensitive Circuits. ASYNC 2015: 45-52 - [c61]Rajit Manohar, Yoram Moses:
Analyzing Isochronic Forks with Potential Causality. ASYNC 2015: 69-76 - [c60]Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar:
AES Hardware-Software Co-design in WSN. ASYNC 2015: 85-92 - [c59]Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar:
Automatic obfuscated cell layout for trusted split-foundry design. HOST 2015: 56-61 - [c58]Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar:
Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications. ISCAS 2015: 2712-2715 - [c57]Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate:
Preventing glitches and short circuits in high-level self-timed chip specifications. PLDI 2015: 270-279 - 2014
- [j11]François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar:
An asymmetric dual-processor architecture for low-power information appliances. ACM Trans. Embed. Comput. Syst. 13(4): 98:1-98:19 (2014) - [c56]Benjamin Z. Tang, Sunil A. Bhave, Rajit Manohar:
Low Power Asynchronous VLSI with NEM Relays. ASYNC 2014: 85-92 - [c55]Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar:
Using asymmetric cores to reduce power consumption for interactive devices with bi-stable displays. CHI 2014: 1059-1062 - [c54]Stephen Longfield Jr., Rajit Manohar:
Removing concurrency for rapid functional verification. ICCAD 2014: 332-339 - [c53]Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar:
ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes. ISQED 2014: 667-674 - [c52]Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha:
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC 2014: 27-38 - 2013
- [c51]Robert Karmazin, Carlos Tadeo Ortega Otero, Rajit Manohar:
cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. ASYNC 2013: 58-66 - [c50]Jonathan Tse, Benjamin Hill, Rajit Manohar:
A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. ASYNC 2013: 124-133 - [c49]Stephen Longfield Jr., Rajit Manohar:
Inverting Martin Synthesis for Verification. ASYNC 2013: 150-157 - [c48]Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar:
A split-foundry asynchronous FPGA. CICC 2013: 1-4 - [c47]Saber Moradi, Nabil Imam, Rajit Manohar, Giacomo Indiveri:
A memory-efficient routing method for large-scale spiking neural networks. ECCTD 2013: 1-4 - [c46]Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, Rajit Manohar:
Neural spiking dynamics in asynchronous digital circuits. IJCNN 2013: 1-8 - 2012
- [j10]Shivam Priyadarshi, T. Robert Harris, Samson Melamed, Carlos Tadeo Ortega Otero, Nikhil Kriplani, Carlos E. Christoffersen, Rajit Manohar, Steven R. Dooley, W. Rhett Davis, Paul D. Franzon, Michael B. Steer:
Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. IET Circuits Devices Syst. 6(1): 35-44 (2012) - [c45]Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha:
A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. ASYNC 2012: 25-32 - [c44]Benjamin Z. Tang, Stephen Longfield Jr., Sunil A. Bhave, Rajit Manohar:
A Low Power Asynchronous GPS Baseband Processor. ASYNC 2012: 33-40 - [c43]Basit Riaz Sheikh, Rajit Manohar:
An Asynchronous Floating-Point Multiplier. ASYNC 2012: 89-96 - [c42]John V. Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez-Icaza, Andrew Cassidy, Shyamal Chandra, Steven K. Esser, Nabil Imam, William P. Risk, Daniel Ben Dayan Rubin, Rajit Manohar, Dharmendra S. Modha:
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core. IJCNN 2012: 1-8 - 2011
- [j9]Basit Riaz Sheikh, Rajit Manohar:
Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits. ACM J. Emerg. Technol. Comput. Syst. 7(4): 19:1-19:26 (2011) - [c41]Nabil Imam, Rajit Manohar:
Address-Event Communication Using Token-Ring Mutual Exclusion. ASYNC 2011: 99-108 - [c40]Paul Merolla, John V. Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha:
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm. CICC 2011: 1-4 - 2010
- [c39]Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar:
Static Power Reduction Techniques for Asynchronous Circuits. ASYNC 2010: 52-61 - [c38]Christopher LaFrieda, Benjamin Hill, Rajit Manohar:
An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. ASYNC 2010: 141-150 - [c37]Basit Riaz Sheikh, Rajit Manohar:
An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder. ASYNC 2010: 151-162
2000 – 2009
- 2009
- [c36]Christopher LaFrieda, Rajit Manohar:
Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. ASYNC 2009: 217-226 - 2008
- [c35]Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra J. Jackson, Rajit Manohar:
Variability in 3-D integrated circuits. CICC 2008: 659-662 - 2007
- [j8]Qing Zhao, Rajit Manohar, Robert J. Ulman, Venugopal V. Veeravalli:
Resource-Constrained Signal Processing, Communications, and Networking [From the Guest Editors]. IEEE Signal Process. Mag. 24(3): 12-14 (2007) - [c34]Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar:
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. DSN 2007: 317-326 - [c33]Alyssa B. Apsel, Rajit Manohar, Alain J. Martin:
Analog and asynchronous variation-aware circuits. ICECS 2007: 1 - 2006
- [c32]Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel:
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. ASYNC 2006: 12-22 - [c31]Song Peng, Rajit Manohar:
Self-Healing Asynchronous Arrays. ASYNC 2006: 34-45 - [c30]Rajit Manohar:
Reconfigurable Asynchronous Logic. CICC 2006: 13-20 - [c29]Song Peng, Rajit Manohar:
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. ACM Great Lakes Symposium on VLSI 2006: 159-164 - [c28]David Fang, Filipp Akopyan, Rajit Manohar:
Self-Timed Thermally-Aware Circuits. ISVLSI 2006: 438-439 - 2005
- [c27]Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar:
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. ASYNC 2005: 144-154 - [c26]Song Peng, Rajit Manohar:
Efficient Failure Detection in Pipelined Asynchronous Circuits. DFT 2005: 484-493 - [c25]David Fang, John Teifel, Rajit Manohar:
A High-Performance Asynchronous FPGA: Test Results. FCCM 2005: 271-272 - [c24]Song Peng, David Fang, John Teifel, Rajit Manohar:
Automated synthesis for asynchronous FPGAs. FPGA 2005: 163-173 - [c23]Song Peng, Rajit Manohar:
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. ICCD 2005: 171-179 - [c22]Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari:
Mapping system-on-chip designs from 2-D to 3-D ICs. ISCAS (3) 2005: 2939-2942 - 2004
- [j7]John Teifel, Rajit Manohar:
An Asynchronous Dataflow FPGA Architecture. IEEE Trans. Computers 53(11): 1376-1392 (2004) - [c21]Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar:
An ultra low-power processor for sensor networks. ASPLOS 2004: 27-36 - [c20]John Teifel, Rajit Manohar:
Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. ASYNC 2004: 17-27 - [c19]David Fang, Rajit Manohar:
Non-Uniform Access Asynchronous Register Files. ASYNC 2004: 75-85 - [c18]Christopher LaFrieda, Rajit Manohar:
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. DSN 2004: 41-50 - [c17]John Teifel, Rajit Manohar:
Highly pipelined asynchronous FPGAs. FPGA 2004: 133-142 - 2003
- [c16]Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar:
SNAP: A Sensor-Network Asynchronous Processor. ASYNC 2003: 24-35 - [c15]John Teifel, Rajit Manohar:
A High-Speed Clockless Serial Link Transceiver. ASYNC 2003: 151-163 - [c14]Virantha N. Ekanayake, Rajit Manohar:
Asynchronous DRAM Design and Synthesis. ASYNC 2003: 174-183 - [c13]Clinton Kelly IV, Rajit Manohar:
An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. DS-RT 2003: 110-119 - [c12]John Teifel, Rajit Manohar:
Programmable Asynchronous Pipeline Arrays. FPL 2003: 345-354 - [c11]Rajit Manohar, Anna Scaglione:
Power optimal routing in wireless networks. ICC 2003: 2979-2984 - 2002
- [c10]Rajit Manohar, Clinton Kelly IV, John Teifel, David Fang, David Biermann:
Energy-Efficient Pipelines. ASYNC 2002: 23-33 - [c9]Rajit Manohar:
Scalable formal design methods for asynchronous VLSI. POPL 2002: 245-246 - 2001
- [j6]Rajit Manohar, Clinton Kelly IV:
Network on a chip: modeling wireless networks with asynchronous VLSI. IEEE Commun. Mag. 39(11): 149-155 (2001) - [c8]Rajit Manohar, Mika Nyström, Alain J. Martin:
Precise Exceptions in Asynchronous Processors. ARVLSI 2001: 16-28 - [c7]Rajit Manohar:
Width-Adaptive Data Word Architectures. ARVLSI 2001: 112-131 - [c6]Rajit Manohar:
An Analysis of Reshuffled Handshaking Expansions. ASYNC 2001: 96-
1990 – 1999
- 1999
- [b1]Rajit Manohar:
The impact of asynchrony on computer architecture. California Institute of Technology, USA, 1999 - [j5]K. Rustan M. Leino, Rajit Manohar:
Joining Specification Statements. Theor. Comput. Sci. 216(1-2): 375-394 (1999) - [j4]Rajit Manohar:
The entropy of traces in parallel computation. IEEE Trans. Inf. Theory 45(5): 1606-1608 (1999) - [c5]Rajit Manohar, Tak-Kwan Lee, Alain J. Martin:
Projection: A Synthesis Technique for Concurrent Systems. ASYNC 1999: 125-134 - 1998
- [j3]Rajit Manohar, José A. Tierno:
Asynchronous Parallel Prefix Computation. IEEE Trans. Computers 47(11): 1244-1252 (1998) - [c4]Rajit Manohar, Alain J. Martin:
Slack Elasticity in Concurrent Computing. MPC 1998: 272-285 - 1997
- [j2]Donald Dabdub, Rajit Manohar:
Performance and Portability of an Air Quality Model. Parallel Comput. 23(14): 2187-2200 (1997) - [c3]Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings:
The Design of an Asynchronous MIPS R3000 Microprocessor. ARVLSI 1997: 164-181 - 1996
- [c2]José A. Tierno, Rajit Manohar, Alain J. Martin:
The energy and entropy of VLSI computations. ASYNC 1996: 188-196 - 1995
- [j1]Rajit Manohar, K. Rustan M. Leino:
Conditional Composition. Formal Aspects Comput. 7(6): 683-703 (1995) - [c1]K. Mani Chandy, Rajit Manohar, Berna L. Massingill, Daniel I. Meiron:
Integrating task and data parallelism with the group communication archetype. IPPS 1995: 724-733
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-21 21:30 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
