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Books and Theses
- 2011
[b1]Thomas B. Preußer:
Increasing the Performance and Predictability of the Code Execution on an Embedded Java Platform (Ansätze zur Steigerung der Leistungsfähigkeit und Vorhersagbarkeit der Codeausführung auf einer eingebetteten Java-Plattform). Dresden University of Technology, 2011
Journal Articles
- 2024
- [j10]Konstantin Hoßfeld
, Hans Jakob Damsgaard, Jari Nurmi, Michaela Blott, Thomas B. Preußer:
High-efficiency Compressor Trees for Latest AMD FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(2): 30:1-30:32 (2024) - 2023
- [j9]Monica Chiosa, Thomas B. Preußer, Michaela Blott, Gustavo Alonso:
AMNES: Accelerating the computation of data correlation using FPGAs. Proc. VLDB Endow. 16(13): 4174-4187 (2023) - [j8]Syed Asad Alam, David Gregg, Giulio Gambardella, Thomas B. Preußer, Michaela Blott:
On the RTL Implementation of FINN Matrix Vector Unit. ACM Trans. Embed. Comput. Syst. 22(6): 94:1-94:27 (2023) - 2022
- [j7]Thomas B. Preußer, Smitha Gautham, Abhi D. Rajagopala, Carl R. Elks, Alexander Weiss:
Everything You Always Wanted to Know About Embedded Trace. Computer 55(2): 34-43 (2022) - 2021
- [j6]Alexander Weiss, Smitha Gautham, Athira Varma Jayakumar, Carl R. Elks, D. Richard Kuhn, Raghu N. Kacker, Thomas B. Preußer:
Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems. Computer 54(1): 49-60 (2021) - [j5]Monica Chiosa, Thomas Preußer, Gustavo Alonso:
SKT: A One-Pass Multi-Sketch Data Analytics Accelerator. Proc. VLDB Endow. 14(11): 2369-2382 (2021) - 2019
- [j4]Matthias R. Engelhardt, Thomas B. Preußer:
An easy counting lemma. Discret. Appl. Math. 257: 175-185 (2019) - [j3]Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander:
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 12(3): 15:1-15:24 (2019) - 2018
- [j2]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers:
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 11(3): 16:1-16:23 (2018) - 2017
- [j1]Thomas B. Preußer, Matthias R. Engelhardt:
Putting Queens in Carry Chains, N o̱27. J. Signal Process. Syst. 88(2): 185-201 (2017)
Conference and Workshop Papers
- 2024
- [c40]Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra:
Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs. FPL 2024: 297-303 - 2021
- [c39]Wenqi Jiang, Zhenhao He, Shuai Zhang, Thomas B. Preußer, Kai Zeng, Liang Feng, Jiansong Zhang, Tongxuan Liu, Yong Li, Jingren Zhou, Ce Zhang, Gustavo Alonso:
MicroRec: Efficient Recommendation Inference by Hardware and Data Structure Solutions. MLSys 2021 - 2020
- [c38]Amit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso:
HyperLogLog Sketch Acceleration on FPGA. FPL 2020: 47-56 - [c37]Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso:
Using DSP Slices as Content-Addressable Update Queues. FPL 2020: 121-126 - 2019
- [c36]Thomas Preußer, Alexander Weiss:
The CEDARtools Platform - Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns. FPL 2019: 426-427 - [c35]Thomas Preußer, Albert Schulz, Alexander Weiss, Martin Heininger, Martin Leucker, Malte Schmitz, Torben Scheffel, Daniel Thoma:
Test und Fehlersuche in komplexen Autonomen Systemen. Echtzeit 2019: 33-42 - 2018
- [c34]Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of quantized neural networks on heterogeneous all-programmable devices. DATE 2018: 833-838 - [c33]Thomas Preußer:
A Brute-Force Solution to the 27-Queens Puzzle Using a Distributed Computation. Int. Conf. on Membrane Computing 2018: 23-29 - 2017
- [c32]Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider:
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. DDECS 2017: 195-200 - [c31]Thomas B. Preußer:
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs. FPL 2017: 1-7 - [c30]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD 2017: 419-422 - 2016
- [c29]Thomas B. Preußer, Martin Zabel, Patrick Lehmann, Rainer G. Spallek:
The portable open-source IP core and utility library PoC. ReConFig 2016: 1-6 - [c28]Thomas B. Preußer, Markus Krause:
Survey on and re-evaluation of wide adder architectures on FPGAs. ReConFig 2016: 1-6 - [c27]Thomas B. Preußer, Fredo Erxleben:
Design Kernel Exploration Using QBF-Based Boolean Matching. SiPS 2016: 219-223 - 2015
- [c26]Kai-Uwe Irrgang, Thomas B. Preußer:
An LZ77-style bit-level compression for trace data compaction. FPL 2015: 1-4 - [c25]Kai-Uwe Irrgang, Thomas B. Preußer, Rainer G. Spallek:
Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. GI-Jahrestagung 2015: 1385-1398 - 2014
- [c24]Thomas B. Preußer, Rainer G. Spallek:
Ready PCIe data streaming solutions for FPGAs. FPL 2014: 1-4 - [c23]Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek:
PoC-align: An open-source alignment accelerator using FPGAs. ReConFig 2014: 1-6 - 2013
- [c22]Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, Rainer G. Spallek:
Weasel: A platform-independent streaming-optimized SATA controller. FPL 2013: 1-4 - 2012
- [c21]Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek:
Short-Read Mapping by a Systolic Custom FPGA Computation. FCCM 2012: 169-176 - [c20]Martin Zabel, Thomas B. Preußer, Rainer G. Spallek:
Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. JTRES 2012: 88-97 - 2011
- [c19]Thomas B. Preußer, Martin Zabel, Rainer G. Spallek:
Accelerating Computations on FPGA Carry Chains by Operand Compaction. IEEE Symposium on Computer Arithmetic 2011: 95-102 - [c18]Oliver Knodel, Thomas B. Preußer, Rainer G. Spallek:
Next-generation massively parallel short-read mapping on FPGAs. ASAP 2011: 195-201 - [c17]Hong Diep Nguyen, Bogdan Pasca, Thomas B. Preußer:
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. FPL 2011: 232-237 - [c16]Marco Kaufmann, Matthias Häsing, Thomas Preußer, Rainer G. Spallek:
The Java Virtual Machine in retargetable, high-performance instruction set simulation. PPPJ 2011: 21-30 - 2010
- [c15]Thomas B. Preußer, Peter Reichel, Rainer G. Spallek:
An Embedded GC Module with Support for Multiple Mutators and Weak References. ARCS 2010: 25-36 - [c14]Thomas B. Preußer, Rainer G. Spallek:
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. FPL 2010: 318-325 - [c13]Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek:
Solving Sudokus through an incidence matrix on an FPGA. FPT 2010: 465-469 - [c12]Martin Schoeberl, Thomas B. Preußer, Sascha Uhrig:
The embedded Java benchmark suite JemBench. JTRES 2010: 120-127 - 2009
- [c11]Thomas B. Preußer, Rainer G. Spallek:
Mapping basic prefix computations to fast carry-chain structures. FPL 2009: 604-608 - [c10]Martin Zabel, Thomas B. Preußer, Rainer G. Spallek:
High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. MBMV 2009: 187-196 - 2008
- [c9]Thomas Preußer, Rainer G. Spallek:
Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. ESA 2008: 260-264 - 2007
- [c8]Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek:
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. DSD 2007: 59-62 - [c7]Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Enabling constant-time interface method dispatch in embedded Java processors. JTRES 2007: 196-205 - [c6]Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Bump-pointer method caching for embedded Java processors. JTRES 2007: 206-210 - 2006
- [c5]Thomas B. Preußer, Rainer G. Spallek:
Analysis of a Fully-Scalable Digital Fractional Clock Divider. ASAP 2006: 173-177 - 2005
- [c4]Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek:
Design space exploration of coarse-grain reconfigurable DSPs. ReConFig 2005 - 2004
- [c3]Thomas Preußer, Steffen Köhler, Rainer G. Spallek:
RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. ESA/VLSI 2004: 130-135 - [c2]Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. FPL 2004: 781-790 - 1998
- [c1]Thomas Preußer:
Prüfsystem VINSPEC für die automatische Qualitätssortierung von Autospiegeln. DAGM-Symposium 1998: 463-470
Informal and Other Publications
- 2023
- [i11]Shivam Aggarwal, Alessandro Pappalardo, Hans Jakob Damsgaard, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra:
Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs. CoRR abs/2311.12359 (2023) - 2021
- [i10]Alexander Weiss, Smitha Gautham, Athira Varma Jayakumar, Carl R. Elks, D. Richard Kuhn, Raghu N. Kacker, Thomas B. Preußer:
Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems. CoRR abs/2102.03420 (2021) - 2020
- [i9]Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso:
Using DSP Slices as Content-Addressable Update Queues. CoRR abs/2004.11080 (2020) - [i8]Amit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso:
HyperLogLog Sketch Acceleration on FPGA. CoRR abs/2005.13332 (2020) - [i7]Wenqi Jiang, Zhenhao He, Shuai Zhang, Thomas B. Preußer, Kai Zeng, Liang Feng, Jiansong Zhang, Tongxuan Liu, Yong Li, Jingren Zhou, Ce Zhang, Gustavo Alonso:
MicroRec: Accelerating Deep Recommendation Systems to Microseconds by Hardware and Data Structure Solutions. CoRR abs/2010.05894 (2020) - 2019
- [i6]Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander:
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. CoRR abs/1901.00370 (2019) - 2018
- [i5]Thomas B. Preußer:
QBM - Mapping User-Specified Functions to Programmable Logic through a QBF Satisfiability Problem. CoRR abs/1801.02075 (2018) - [i4]Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices. CoRR abs/1806.08085 (2018) - [i3]Thomas B. Preußer:
Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs. CoRR abs/1806.08095 (2018) - [i2]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR abs/1807.03123 (2018) - [i1]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu:
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. CoRR abs/1809.04570 (2018)
Coauthor Index
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