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ORCIDTom Chen 0001
Thomas Chen 0001 – Tom W. Chen – Thomas W. Chen
Person information
- affiliation: Colorado State University, Department of Electrical and Computer Engineering, Fort Collins, CO, USA
Other persons with the same name
- Tom Chen — disambiguation page
- Tom Chen 0002 (aka: Thomas W. Y. Chen, Thomas Wen-Yao Chen) — Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan
- Thomas M. Chen
![[0000-0001-8037-1685]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8037-1685")
(aka: Tom Chen 0003) — City University of London, Department of Electrical & Electronic Engineering, UK (and 4 more) - Thomas Chen — disambiguation page
- Thomas Chen 0002 — Johns Hopkins University, Baltimore, MD, USA
- Thomas Chen 0003 — University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA
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Journal Articles
- 2020
[j30]William Tedjo, Thomas W. Chen:
An Integrated Biosensor System With a High-Density Microelectrode Array for Real-Time Electrochemical Imaging. IEEE Trans. Biomed. Circuits Syst. 14(1): 20-35 (2020)- [j29]Caleb Begly, David Ackart, Julian Mylius, Randall Basaraba, Adam J. Chicco, Thomas W. Chen:
Study of Real-Time Spatial and Temporal Behavior of Bacterial Biofilms Using 2-D Impedance Spectroscopy. IEEE Trans. Biomed. Circuits Syst. 14(5): 1051-1064 (2020) - 2017
- [j28]Anthony A. Maciejewski, Thomas W. Chen, Zinta S. Byrne, Michael A. De Miranda, Laura B. Sample Mcmeeking, Branislav M. Notaros, Ali Pezeshki, Sourajeet Roy, Andrea M. Leland, Melissa D. Reese, Alma H. Rosales, Thomas J. Siller, Richard F. Toftness, Olivera Notaros:
A Holistic Approach to Transforming Undergraduate Electrical Engineering Education. IEEE Access 5: 8148-8161 (2017) - 2016
- [j27]Yishai Statter, Tom Chen:
A novel high-throughput method for table look-up based analog design automation. Integr. 52: 168-181 (2016) - [j26]Yishai Statter, Tom Chen:
Γ (Gamma): A SaaS-enabled fast and accurate analog design System. Integr. 55: 67-84 (2016) - [j25]Mozammel Hossain, John Badar, Jack DiLullo, Tom Chen:
A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis. Microprocess. Microsystems 45: 241-252 (2016) - 2015
- [j24]Mozammel Hossain, Chirag Desai, Tom Chen, Vikas Agarwal:
Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design. Integr. 49: 125-136 (2015) - 2010
- [j23]Charles Thangaraj, Alkan Cengiz, Tom Chen:
Rapid design space exploration using legacy design data and technology scaling trend. Integr. 43(2): 202-219 (2010) - [j22]Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen:
Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1385-1398 (2010) - 2007
- [j21]Daniela De Venuto, Tom Chen:
Editorial. Microelectron. J. 38(4-5): 453 (2007) - [j20]Justin Gregg, Tom W. Chen:
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 366-376 (2007) - 2005
- [j19]Daniela De Venuto, Tom Chen:
International Symposium on Quality Electronic Design. Microelectron. J. 36(9): 787-788 (2005) - [j18]Medha Kulkarni, Tom Chen:
A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1336-1346 (2005) - 2004
- [j17]Geun Rae Cho, Tom Chen:
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 229-242 (2004) - [j16]Tom Chen, Amjad Hajjar:
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1677-1683 (2004) - [j15]Gerald Esch Jr., Tom Chen:
Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1253-1257 (2004) - 2003
- [j14]Jinsang Kim, Tom Chen:
A VLSI architecture for video-object segmentation. IEEE Trans. Circuits Syst. Video Technol. 13(1): 83-96 (2003) - 2002
- [j13]Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson:
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. J. Electron. Test. 18(6): 583-594 (2002) - 2001
- [j12]Jinsang Kim, Tom Chen:
Multiple feature clustering for image sequence segmentation. Pattern Recognit. Lett. 22(11): 1207-1217 (2001) - [j11]Geun Rae Cho, Tom Chen:
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. VLSI Design 12(3): 399-406 (2001) - 1999
- [j10]Ytong-Bin Kim, Tom W. Chen:
Assessing merged DRAM/Logic technology. Integr. 27(2): 179-194 (1999) - [j9]Amjad Hajjar, Tom Chen:
VLSI Architecture for Real-Time Edge Linking. IEEE Trans. Pattern Anal. Mach. Intell. 21(1): 89-94 (1999) - [j8]Von-Kyoung Kim, Tom Chen:
On comparing functional fault coverage and defect coverage for memory testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1676-1683 (1999) - [j7]Tom Chen, Glen Sunada, Jain Jin:
COBRA: a 100-MOPS single-chip programmable and expandable FFT. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 174-182 (1999) - 1997
- [j6]Mick Tegethoff, Tom Chen:
Simulation Techniques for the Manufacturing Test of MCMs. J. Electron. Test. 10(1-2): 137-149 (1997) - [j5]Fahad M. Alzahrani, Tom Chen:
A Real-Time Edge Detector: Algorithm and VLSI Architecture. Real Time Imaging 3(5): 363-378 (1997) - 1996
- [j4]Mick Tegethoff, Tom Chen:
Sensitivity Analysis of Critical Parameters in Board Test. IEEE Des. Test Comput. 13(1): 58-63 (1996) - 1995
- [j3]Xiao-Dong Wang, Tom Chen:
Performance and Area Optimization of VLSI Systems Using Genetic Algorithms. VLSI Design 3(1): 43-51 (1995) - 1993
- [j2]Tom Chen, Glen Sunada:
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. IEEE Trans. Very Large Scale Integr. Syst. 1(2): 88-97 (1993) - [j1]Tom Chen, Li Zhu:
An expandable column fft architecture using circuit switching networks. J. VLSI Signal Process. 6(3): 243-257 (1993)
Conference and Workshop Papers
- 2017
- [c76]Lang Yang, Tom Chen:
A handheld electrochemical sensing platform for point-of-care diagnostic applications. BioCAS 2017: 1-4 - 2016
- [c75]William Tedjo, Rachel Feeny, Chad Eitel, Luke Schwerdtfeger, Stacy Willett, Charles Henry, Stuart Tobet, Tom Chen:
Design of an integrated microelectrode array system for high spatiotemporal resolution chemical imaging. BioCAS 2016: 46-49 - [c74]Lang Yang, Tom Chen:
A compact signal generation and acquisition circuit for electrochemical impedance spectroscopy. BioCAS 2016: 260-263 - [c73]Abhiram Reddy Gundla, Tom Chen:
A 0.2 nJ/bit QPSK transmitter with tuning for process variation for biomedical telemetry in the MedRadio band of 401-457 MHz. MWSCAS 2016: 1-4 - [c72]Abhiram Reddy Gundla, Tom Chen:
An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz. VLSI-SoC 2016: 1-5 - 2015
- [c71]Lang Yang, Thomas W. Chen:
A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical Applications. DSD 2015: 383-389 - [c70]Abhiram Reddy Gundla, Tom Chen:
A low power frequency synthesizer for biosensor applications in the MedRadio band. MWSCAS 2015: 1-4 - 2014
- [c69]William Wilson, Tom Chen:
Design of a 50MΩ Transimpedance Amplifier with 0.98fa/vHz Input Inferred Noise in a 0.18µM CMOS Technology. BIODEVICES 2014: 112-119 - [c68]Hai Chi, Tom Chen:
A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C. ISVLSI 2014: 261-266 - 2013
- [c67]Ryan Selby, Tom Chen:
A 2nd Order CMOS Sigma-Delta Modulator Design Suitable for Low-Power Biosensor Applications. BIOSTEC (Selected Papers) 2013: 3-12 - [c66]Ryan Selby, Tom Chen:
A 0.18µm CMOS 2nd Order Sigma-Delta Modulator for Low-power Biosensor Applications. BIODEVICES 2013: 5-9 - [c65]Kristin Scholfield, Tom Chen:
A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications. DSD 2013: 689-694 - [c64]Ryan Selby, Kern Tucker, William Wilson, Tom Chen:
A 0.18µm CMOS switched-capacitor amplifier using current-starving inverter based op-amp for low-power biosensor applications. LASCAS 2013: 1-4 - [c63]William Wilson, Tom Chen, Ryan Selby:
A current-starved inverter-based differential amplifier design for ultra-low power applications. LASCAS 2013: 1-4 - 2010
- [c62]Chandrika Jena, Tim Mason, Tom Chen:
On power and performance tradeoff of L2 cache compression. APCCAS 2010: 724-727 - [c61]Allen Chen, Ryan Hoppal, Tom Chen:
On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. DSD 2010: 628-634 - [c60]Zach Cashero, Allen Chen, Ryan Hoppal, Tom Chen:
Fast Evaluation of Analog Circuits Using Linear Programming. ISVLSI 2010: 253-258 - 2008
- [c59]Charles Thangaraj, Tom Chen:
Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. DELTA 2008: 539-544 - [c58]Tsau-Shuan Wu, Alkan Cengiz, Tom W. Chen:
Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking. DSD 2008: 535-541 - [c57]Charles Thangaraj, Tom Chen:
Design target exploration for meeting time-to-market using pareto analysis. ISCAS 2008: 364-367 - 2007
- [c56]Vaibhav Nawale, Thomas W. Chen:
Steady state noise modeling in computer chips using neural networks. Artificial Intelligence and Applications 2007: 19-24 - [c55]Charles Thangaraj, Tom Chen:
Power andPerformance Analysis for Early Design Space Exploration. ISVLSI 2007: 473-478 - 2006
- [c54]Jayashree Sridharan, Tom Chen:
Modeling multiple input switching of CMOS gates in DSM technology using HDMR. DATE 2006: 626-631 - [c53]Vaibhav Nawale, Thomas W. Chen:
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations. ICCAD 2006: 27-32 - [c52]Alkan Cengiz, Tom W. Chen:
Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization. ISVLSI 2006: 367-372 - [c51]Jayashree Sridharan, Tom Chen:
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. VLSI Design 2006: 323-328 - [c50]Alkan Cengiz, Tom W. Chen:
A Progressive Two-Stage Global Routing for Macro-Cell Based Designs. VLSI Design 2006: 777-780 - 2005
- [c49]Vinil Varghese, Tom Chen, Peter Michael Young:
Stability analysis of active clock deskewing systems using a control theoretic approach. ACC 2005: 1758-1763 - [c48]Vinil Varghese, Tom Chen, Peter Michael Young:
Stability analysis of active clock deskewing systems using a control theoretic approach. ASP-DAC 2005: 600-605 - [c47]Vinil Varghese, Tom Chen, Peter Michael Young:
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. DATE 2005: 820-825 - [c46]Ajith Chandy, Tom Chen:
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. DATE 2005: 984-985 - [c45]Justin Gregg, Tom W. Chen:
Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm. ISQED 2005: 297-302 - [c44]Justin Gregg, Tom W. Chen:
PEER: Enriching Secondary Engineering Education Through a College Summer Camp. MSE 2005: 109-110 - 2004
- [c43]Tom W. Chen, Justin Gregg:
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations. DATE 2004: 240-245 - [c42]Gerald Esch Jr., Tom Chen:
Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. DELTA 2004: 312-320 - [c41]Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen:
RUBASTEM: A Method for Testing VHDL Behavioral Models. HASE 2004: 187-196 - [c40]Medha Kulkarni, Tom Chen:
A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. ISQED 2004: 331-336 - [c39]Justin Gregg, Tom W. Chen:
Post Silicon Power/Performance Optimization in the Presence of ProcessVariations Using Individual Well Adaptive Body Biasing (IWABB). ISQED 2004: 453-458 - 2003
- [c38]Chetan Despande, Tom Chen:
Design of a CMOS test chip for package models and I/O characteristics verification. ASP-DAC 2003: 565-566 - [c37]Geun Rae Cho, Tom Chen:
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED 2003: 55-60 - [c36]Tom Chen, Amjad Hajjar:
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. ISQED 2003: 183-188 - [c35]Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen:
A Rule-Based Software Testing Method for VHDL Models. VLSI-SOC 2003: 92- - [c34]Geun Rae Cho, Tom Chen:
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design 2003: 513- - 2002
- [c33]Amjad Hajjar, Tom Chen:
An Accurate Coverage Forecasting Model for Behavioral Model Verification. DELTA 2002: 104-110 - [c32]Geun Rae Cho, Tom Chen:
On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD 2002: 322-326 - [c31]Amjad Hajjar, Tom Chen:
Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. ISQED 2002: 304-309 - [c30]Geun Rae Cho, Tom Chen:
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED 2002: 458-463 - [c29]Geun Rae Cho, Tom Chen:
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294 - [c28]Geun Rae Cho, Tom Chen:
Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. SEAL 2002: 446-465 - 2001
- [c27]Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman:
High quality behavioral verification using statistical stopping criteria. DATE 2001: 411-419 - [c26]Tom Chen:
On the impact of on-chip inductance on signal nets under the influence of power grid noise. DATE 2001: 451-459 - [c25]Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman:
Stopping Criteria Comparison: Towards High Quality Behavioral Verification. ISQED 2001: 31-37 - [c24]Tom Chen:
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. ISQED 2001: 173-178 - [c23]Jinsang Kim, Tom Chen:
Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. VIIP 2001: 483-488 - 2000
- [c22]Jinsang Kim, Tom Chen:
A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. CAMP 2000: 57- - [c21]Tom W. Chen, Alkan Cengiz:
Measuring routing congestion for multi-layer global routing. ACM Great Lakes Symposium on VLSI 2000: 59-62 - [c20]Amjad Hajjar, Tom Chen, Anneliese von Mayrhauser:
On statistical behavior of branch coverage in testing behavioral VHDL models. HLDVT 2000: 89-94 - [c19]Anneliese von Mayrhauser, Tom Chen, Jan Kok, Chuck Anderson, Anita Read, Amjad Hajjar:
On choosing test criteria for behavioral level hardware design verification. HLDVT 2000: 124-130 - [c18]Jinsang Kim, Tom Chen:
Segmentation of Image Sequences Using SOFM Networks. ICPR 2000: 3877-3880 - [c17]Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu:
Achieving the Quality of Verification for Behavioral Models with Minimum Effort. ISQED 2000: 234- - 1999
- [c16]Von-Kyoung Kim, Tom Chen, Mick Tegethoff:
Fault Coverage Estimation for Early Stage of VLSI Design. Great Lakes Symposium on VLSI 1999: 105-108 - [c15]Von-Kyoung Kim, Tom Chen:
Assessing Defect Coverage of Memory Testing Algorithms. Great Lakes Symposium on VLSI 1999: 340- - [c14]Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu:
How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. HASE 1999: 249-256 - [c13]Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar:
Efficient Verification of Behavioral Models Using Sequential Sampling Technique. VLSI 1999: 398-406 - 1998
- [c12]Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar:
Fast Antirandom (FAR) Test Generation. HASE 1998: 262-269 - 1997
- [c11]Fahad M. Alzahrani, Tom Chen:
A real-time high performance edge detector for computer vision applications. ASP-DAC 1997: 671-672 - [c10]Von-Kyoung Kim, Tom Chen, Mick Tegethoff:
ASIC Manufacturing Test Cost Prediction at Early Design Stage. ITC 1997: 356-361 - 1996
- [c9]Von-Kyoung Kim, Mick Tegethoff, Tom Chen:
ASIC Yield Estimation at Early Design Cycle. ITC 1996: 590-594 - [c8]Charles Anderson, Anneliese von Mayrhauser, Tom Chen:
Assessing Neural Networks as Guides for Testing Activities. IEEE METRICS 1996: 155-165 - 1994
- [c7]Fahad M. Alzahrani, Tom Chen:
On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. ICCD 1994: 132-137 - [c6]Glen Sunada, Jain Jin, Matt Berzins, Tom Chen:
COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. ICCD 1994: 546-550 - [c5]Mick Tegethoff, Tom Chen:
Defects, Fault Coverage, Yield and Cost in Board Manufacturing. ITC 1994: 539-547 - [c4]Mick Tegethoff, Tom Chen:
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. ITC 1994: 903-910 - 1992
- [c3]Tom Chen, Glen Sunada:
An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. ICCD 1992: 576-581 - [c2]Tom Chen, Glen Sunada:
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. ITC 1992: 623-631 - 1991
- [c1]Tom Chen, Li Zhu:
A Fast 1024-Point FFT Architecture. ICPP (1) 1991: 646-647
Coauthor Index
Anneliese Amschler Andrews
aka: Anneliese von Mayrhauser
aka: Anneliese von Mayrhauser
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